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47ac0f0c7c
instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
3.0 KiB
C++
92 lines
3.0 KiB
C++
//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation for instruction scheduler function
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// pass registry (RegisterScheduler).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
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#define LLVM_CODEGENSCHEDULERREGISTRY_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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namespace llvm {
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//===----------------------------------------------------------------------===//
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///
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/// RegisterScheduler class - Track the registration of instruction schedulers.
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///
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//===----------------------------------------------------------------------===//
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class SelectionDAGISel;
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class ScheduleDAGSDNodes;
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class SelectionDAG;
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class MachineBasicBlock;
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class RegisterScheduler : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
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static MachinePassRegistry Registry;
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RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C)
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{ Registry.Add(this); }
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~RegisterScheduler() { Registry.Remove(this); }
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// Accessors.
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//
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RegisterScheduler *getNext() const {
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return (RegisterScheduler *)MachinePassRegistryNode::getNext();
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}
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static RegisterScheduler *getList() {
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return (RegisterScheduler *)Registry.getList();
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}
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static FunctionPassCtor getDefault() {
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return (FunctionPassCtor)Registry.getDefault();
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}
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static void setDefault(FunctionPassCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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/// reduction list scheduler.
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ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
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bool Fast);
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/// createTDRRListDAGScheduler - This creates a top down register usage
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/// reduction list scheduler.
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ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
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bool Fast);
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/// createTDListDAGScheduler - This creates a top-down list scheduler with
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/// a hazard recognizer.
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ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
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bool Fast);
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/// createFastDAGScheduler - This creates a "fast" scheduler.
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///
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ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
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bool Fast);
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
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bool Fast);
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} // end namespace llvm
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#endif
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