Vincent Lejeune 4ed9917147 R600: Relax some vector constraints on Dot4. ...

Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-17 16:50:32 +00:00

..

AArch64

More test coverage for addFrameMove.

2013-05-16 20:50:56 +00:00

ARM

ARM ISel: Don't create illegal types during LowerMUL

2013-05-14 22:33:24 +00:00

CPP

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Generic

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Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

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MBlaze

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Mips

[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).

2013-05-16 21:17:15 +00:00

MSP430

DAGCombiner: Simplify inverted bit tests

2013-05-08 06:44:42 +00:00

NVPTX

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PowerPC

Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.ll

2013-05-16 20:28:05 +00:00

R600

R600: Relax some vector constraints on Dot4.

2013-05-17 16:50:32 +00:00

SI

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SPARC

[Sparc] Implements hasReservedCallFrame and hasFP.

2013-05-17 15:14:34 +00:00

SystemZ

[SystemZ] Make use of SUBTRACT HALFWORD

2013-05-15 15:05:29 +00:00

Thumb

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Thumb2

Fix ARM FastISel tests, as a first step to enabling ARM FastISel

2013-05-14 16:26:38 +00:00

X86

X86: Make shuffle -> shift conversion more aggressive about undefs.

2013-05-17 14:48:34 +00:00

XCore

[XCore] Fix handling of functions where only the LR is spilled.

2013-05-09 16:43:42 +00:00