mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a347f85dbe
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
966 lines
34 KiB
C++
966 lines
34 KiB
C++
//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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// This file is responsible for the frame pointer elimination optimization
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// on X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/CommandLine.h"
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#include "X86GenRegisterDesc.inc"
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#include "X86GenRegisterInfo.inc"
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using namespace llvm;
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cl::opt<bool>
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ForceStackAlign("force-align-stack",
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cl::desc("Force align the stack to the minimum alignment"
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" needed for the function."),
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cl::init(false), cl::Hidden);
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X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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const TargetInstrInfo &tii)
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: X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
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tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKDOWN64 :
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X86::ADJCALLSTACKDOWN32,
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tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKUP64 :
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X86::ADJCALLSTACKUP32),
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TM(tm), TII(tii) {
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// Cache some information.
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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Is64Bit = Subtarget->is64Bit();
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IsWin64 = Subtarget->isTargetWin64();
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if (Is64Bit) {
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SlotSize = 8;
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StackPtr = X86::RSP;
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FramePtr = X86::RBP;
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} else {
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SlotSize = 4;
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StackPtr = X86::ESP;
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FramePtr = X86::EBP;
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}
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}
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static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
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if (!Subtarget->is64Bit()) {
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if (Subtarget->isTargetDarwin()) {
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if (isEH)
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return DWARFFlavour::X86_32_DarwinEH;
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else
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return DWARFFlavour::X86_32_Generic;
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} else if (Subtarget->isTargetCygMing()) {
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// Unsupported by now, just quick fallback
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return DWARFFlavour::X86_32_Generic;
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} else {
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return DWARFFlavour::X86_32_Generic;
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}
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}
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return DWARFFlavour::X86_64;
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}
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/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
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/// specific numbering, used in debug info and exception tables.
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int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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unsigned Flavour = getFlavour(Subtarget, isEH);
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return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
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}
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/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
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int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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unsigned Flavour = getFlavour(Subtarget, isEH);
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return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
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}
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int
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X86RegisterInfo::getSEHRegNum(unsigned i) const {
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int reg = getX86RegNum(i);
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switch (i) {
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
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case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
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case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
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case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
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reg += 8;
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}
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return reg;
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}
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/// getX86RegNum - This function maps LLVM register identifiers to their X86
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/// specific numbering, which is used in various places encoding instructions.
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unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
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return N86::ESP;
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case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
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return N86::EBP;
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case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
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return N86::ESI;
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case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
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return N86::EDI;
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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return N86::EAX;
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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return N86::ECX;
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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return N86::EDX;
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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return N86::EBX;
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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return N86::ESP;
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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return N86::EBP;
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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return N86::ESI;
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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return N86::EDI;
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case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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case X86::XMM0: case X86::XMM8:
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case X86::YMM0: case X86::YMM8: case X86::MM0:
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return 0;
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case X86::XMM1: case X86::XMM9:
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case X86::YMM1: case X86::YMM9: case X86::MM1:
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return 1;
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case X86::XMM2: case X86::XMM10:
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case X86::YMM2: case X86::YMM10: case X86::MM2:
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return 2;
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case X86::XMM3: case X86::XMM11:
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case X86::YMM3: case X86::YMM11: case X86::MM3:
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return 3;
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case X86::XMM4: case X86::XMM12:
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case X86::YMM4: case X86::YMM12: case X86::MM4:
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return 4;
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case X86::XMM5: case X86::XMM13:
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case X86::YMM5: case X86::YMM13: case X86::MM5:
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return 5;
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case X86::XMM6: case X86::XMM14:
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case X86::YMM6: case X86::YMM14: case X86::MM6:
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return 6;
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case X86::XMM7: case X86::XMM15:
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case X86::YMM7: case X86::YMM15: case X86::MM7:
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return 7;
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case X86::ES: return 0;
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case X86::CS: return 1;
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case X86::SS: return 2;
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case X86::DS: return 3;
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case X86::FS: return 4;
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case X86::GS: return 5;
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case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
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case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
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case X86::CR2: case X86::CR10: case X86::DR2: return 2;
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case X86::CR3: case X86::CR11: case X86::DR3: return 3;
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case X86::CR4: case X86::CR12: case X86::DR4: return 4;
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case X86::CR5: case X86::CR13: case X86::DR5: return 5;
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case X86::CR6: case X86::CR14: case X86::DR6: return 6;
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case X86::CR7: case X86::CR15: case X86::DR7: return 7;
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// Pseudo index registers are equivalent to a "none"
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// scaled index (See Intel Manual 2A, table 2-3)
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case X86::EIZ:
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case X86::RIZ:
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return 4;
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default:
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assert(isVirtualRegister(RegNo) && "Unknown physical register!");
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llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
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return 0;
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}
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}
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const TargetRegisterClass *
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X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned SubIdx) const {
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switch (SubIdx) {
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default: return 0;
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case X86::sub_8bit:
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if (B == &X86::GR8RegClass) {
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if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
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return A;
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} else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
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A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_ABCDRegClass;
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} else if (B == &X86::GR8_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR32_ABCDRegClass;
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else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
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return &X86::GR16_NOREXRegClass;
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else if (A == &X86::GR16_ABCDRegClass)
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return &X86::GR16_ABCDRegClass;
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}
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break;
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case X86::sub_8bit_hi:
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if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
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switch (A->getSize()) {
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case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
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case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
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case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
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default: return 0;
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}
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break;
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case X86::sub_16bit:
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if (B == &X86::GR16RegClass) {
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if (A->getSize() == 4 || A->getSize() == 8)
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return A;
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} else if (B == &X86::GR16_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
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A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_ABCDRegClass;
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} else if (B == &X86::GR16_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
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A == &X86::GR32_NOSPRegClass)
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return &X86::GR32_NOREXRegClass;
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else if (A == &X86::GR32_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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}
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break;
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case X86::sub_32bit:
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if (B == &X86::GR32RegClass) {
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if (A->getSize() == 8)
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return A;
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} else if (B == &X86::GR32_NOSPRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
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return &X86::GR64_NOSPRegClass;
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if (A->getSize() == 8)
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return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
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} else if (B == &X86::GR32_ABCDRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
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A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass ||
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A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_ABCDRegClass;
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} else if (B == &X86::GR32_NOREXRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
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return &X86::GR64_NOREXRegClass;
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else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREX_NOSPRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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} else if (B == &X86::GR32_NOREX_NOSPRegClass) {
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if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
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A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
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return &X86::GR64_NOREX_NOSPRegClass;
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else if (A == &X86::GR64_ABCDRegClass)
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return &X86::GR64_ABCDRegClass;
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}
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break;
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case X86::sub_ss:
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if (B == &X86::FR32RegClass)
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return A;
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break;
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case X86::sub_sd:
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if (B == &X86::FR64RegClass)
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return A;
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break;
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case X86::sub_xmm:
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if (B == &X86::VR128RegClass)
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return A;
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break;
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}
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return 0;
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}
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const TargetRegisterClass*
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X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
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const TargetRegisterClass *Super = RC;
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TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
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do {
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switch (Super->getID()) {
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case X86::GR8RegClassID:
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case X86::GR16RegClassID:
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case X86::GR32RegClassID:
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case X86::GR64RegClassID:
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case X86::FR32RegClassID:
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case X86::FR64RegClassID:
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case X86::RFP32RegClassID:
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case X86::RFP64RegClassID:
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case X86::RFP80RegClassID:
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case X86::VR128RegClassID:
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case X86::VR256RegClassID:
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// Don't return a super-class that would shrink the spill size.
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// That can happen with the vector and float classes.
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if (Super->getSize() == RC->getSize())
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return Super;
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}
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Super = *I++;
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} while (Super);
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return RC;
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}
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const TargetRegisterClass *
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X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
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switch (Kind) {
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default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
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case 0: // Normal GPRs.
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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return &X86::GR64RegClass;
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return &X86::GR32RegClass;
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case 1: // Normal GPRs except the stack pointer (for encoding reasons).
|
|
if (TM.getSubtarget<X86Subtarget>().is64Bit())
|
|
return &X86::GR64_NOSPRegClass;
|
|
return &X86::GR32_NOSPRegClass;
|
|
case 2: // Available for tailcall (not callee-saved GPRs).
|
|
if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
|
|
return &X86::GR64_TCW64RegClass;
|
|
if (TM.getSubtarget<X86Subtarget>().is64Bit())
|
|
return &X86::GR64_TCRegClass;
|
|
return &X86::GR32_TCRegClass;
|
|
}
|
|
}
|
|
|
|
const TargetRegisterClass *
|
|
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
|
if (RC == &X86::CCRRegClass) {
|
|
if (Is64Bit)
|
|
return &X86::GR64RegClass;
|
|
else
|
|
return &X86::GR32RegClass;
|
|
}
|
|
return RC;
|
|
}
|
|
|
|
unsigned
|
|
X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
|
|
switch (RC->getID()) {
|
|
default:
|
|
return 0;
|
|
case X86::GR32RegClassID:
|
|
return 4 - FPDiff;
|
|
case X86::GR64RegClassID:
|
|
return 12 - FPDiff;
|
|
case X86::VR128RegClassID:
|
|
return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
|
|
case X86::VR64RegClassID:
|
|
return 4;
|
|
}
|
|
}
|
|
|
|
const unsigned *
|
|
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
|
|
bool callsEHReturn = false;
|
|
bool ghcCall = false;
|
|
|
|
if (MF) {
|
|
callsEHReturn = MF->getMMI().callsEHReturn();
|
|
const Function *F = MF->getFunction();
|
|
ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
|
|
}
|
|
|
|
static const unsigned GhcCalleeSavedRegs[] = {
|
|
0
|
|
};
|
|
|
|
static const unsigned CalleeSavedRegs32Bit[] = {
|
|
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
|
|
};
|
|
|
|
static const unsigned CalleeSavedRegs32EHRet[] = {
|
|
X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
|
|
};
|
|
|
|
static const unsigned CalleeSavedRegs64Bit[] = {
|
|
X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
|
|
};
|
|
|
|
static const unsigned CalleeSavedRegs64EHRet[] = {
|
|
X86::RAX, X86::RDX, X86::RBX, X86::R12,
|
|
X86::R13, X86::R14, X86::R15, X86::RBP, 0
|
|
};
|
|
|
|
static const unsigned CalleeSavedRegsWin64[] = {
|
|
X86::RBX, X86::RBP, X86::RDI, X86::RSI,
|
|
X86::R12, X86::R13, X86::R14, X86::R15,
|
|
X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
|
|
X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
|
|
X86::XMM14, X86::XMM15, 0
|
|
};
|
|
|
|
if (ghcCall) {
|
|
return GhcCalleeSavedRegs;
|
|
} else if (Is64Bit) {
|
|
if (IsWin64)
|
|
return CalleeSavedRegsWin64;
|
|
else
|
|
return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
|
|
} else {
|
|
return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
|
|
}
|
|
}
|
|
|
|
BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|
BitVector Reserved(getNumRegs());
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
// Set the stack-pointer register and its aliases as reserved.
|
|
Reserved.set(X86::RSP);
|
|
Reserved.set(X86::ESP);
|
|
Reserved.set(X86::SP);
|
|
Reserved.set(X86::SPL);
|
|
|
|
// Set the instruction pointer register and its aliases as reserved.
|
|
Reserved.set(X86::RIP);
|
|
Reserved.set(X86::EIP);
|
|
Reserved.set(X86::IP);
|
|
|
|
// Set the frame-pointer register and its aliases as reserved if needed.
|
|
if (TFI->hasFP(MF)) {
|
|
Reserved.set(X86::RBP);
|
|
Reserved.set(X86::EBP);
|
|
Reserved.set(X86::BP);
|
|
Reserved.set(X86::BPL);
|
|
}
|
|
|
|
// Mark the x87 stack registers as reserved, since they don't behave normally
|
|
// with respect to liveness. We don't fully model the effects of x87 stack
|
|
// pushes and pops after stackification.
|
|
Reserved.set(X86::ST0);
|
|
Reserved.set(X86::ST1);
|
|
Reserved.set(X86::ST2);
|
|
Reserved.set(X86::ST3);
|
|
Reserved.set(X86::ST4);
|
|
Reserved.set(X86::ST5);
|
|
Reserved.set(X86::ST6);
|
|
Reserved.set(X86::ST7);
|
|
|
|
// Mark the segment registers as reserved.
|
|
Reserved.set(X86::CS);
|
|
Reserved.set(X86::SS);
|
|
Reserved.set(X86::DS);
|
|
Reserved.set(X86::ES);
|
|
Reserved.set(X86::FS);
|
|
Reserved.set(X86::GS);
|
|
|
|
// Reserve the registers that only exist in 64-bit mode.
|
|
if (!Is64Bit) {
|
|
// These 8-bit registers are part of the x86-64 extension even though their
|
|
// super-registers are old 32-bits.
|
|
Reserved.set(X86::SIL);
|
|
Reserved.set(X86::DIL);
|
|
Reserved.set(X86::BPL);
|
|
Reserved.set(X86::SPL);
|
|
|
|
for (unsigned n = 0; n != 8; ++n) {
|
|
// R8, R9, ...
|
|
const unsigned GPR64[] = {
|
|
X86::R8, X86::R9, X86::R10, X86::R11,
|
|
X86::R12, X86::R13, X86::R14, X86::R15
|
|
};
|
|
for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
|
|
Reserved.set(Reg);
|
|
|
|
// XMM8, XMM9, ...
|
|
assert(X86::XMM15 == X86::XMM8+7);
|
|
for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
|
|
++AI)
|
|
Reserved.set(Reg);
|
|
}
|
|
}
|
|
|
|
return Reserved;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Stack Frame Processing methods
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
return (RealignStack &&
|
|
!MFI->hasVarSizedObjects());
|
|
}
|
|
|
|
bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const Function *F = MF.getFunction();
|
|
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
|
|
bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
|
|
F->hasFnAttr(Attribute::StackAlignment));
|
|
|
|
// FIXME: Currently we don't support stack realignment for functions with
|
|
// variable-sized allocas.
|
|
// FIXME: It's more complicated than this...
|
|
if (0 && requiresRealignment && MFI->hasVarSizedObjects())
|
|
report_fatal_error(
|
|
"Stack realignment in presence of dynamic allocas is not supported");
|
|
|
|
// If we've requested that we force align the stack do so now.
|
|
if (ForceStackAlign)
|
|
return canRealignStack(MF);
|
|
|
|
return requiresRealignment && canRealignStack(MF);
|
|
}
|
|
|
|
bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|
unsigned Reg, int &FrameIdx) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
if (Reg == FramePtr && TFI->hasFP(MF)) {
|
|
FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
|
|
if (is64Bit) {
|
|
if (isInt<8>(Imm))
|
|
return X86::SUB64ri8;
|
|
return X86::SUB64ri32;
|
|
} else {
|
|
if (isInt<8>(Imm))
|
|
return X86::SUB32ri8;
|
|
return X86::SUB32ri;
|
|
}
|
|
}
|
|
|
|
static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
|
|
if (is64Bit) {
|
|
if (isInt<8>(Imm))
|
|
return X86::ADD64ri8;
|
|
return X86::ADD64ri32;
|
|
} else {
|
|
if (isInt<8>(Imm))
|
|
return X86::ADD32ri8;
|
|
return X86::ADD32ri;
|
|
}
|
|
}
|
|
|
|
void X86RegisterInfo::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
|
|
int Opcode = I->getOpcode();
|
|
bool isDestroy = Opcode == getCallFrameDestroyOpcode();
|
|
DebugLoc DL = I->getDebugLoc();
|
|
uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
|
|
uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
|
|
I = MBB.erase(I);
|
|
|
|
if (!reseveCallFrame) {
|
|
// If the stack pointer can be changed after prologue, turn the
|
|
// adjcallstackup instruction into a 'sub ESP, <amt>' and the
|
|
// adjcallstackdown instruction into 'add ESP, <amt>'
|
|
// TODO: consider using push / pop instead of sub + store / add
|
|
if (Amount == 0)
|
|
return;
|
|
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
// alignment boundary.
|
|
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
|
|
Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
|
|
|
|
MachineInstr *New = 0;
|
|
if (Opcode == getCallFrameSetupOpcode()) {
|
|
New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
|
|
StackPtr)
|
|
.addReg(StackPtr)
|
|
.addImm(Amount);
|
|
} else {
|
|
assert(Opcode == getCallFrameDestroyOpcode());
|
|
|
|
// Factor out the amount the callee already popped.
|
|
Amount -= CalleeAmt;
|
|
|
|
if (Amount) {
|
|
unsigned Opc = getADDriOpcode(Is64Bit, Amount);
|
|
New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
|
|
.addReg(StackPtr).addImm(Amount);
|
|
}
|
|
}
|
|
|
|
if (New) {
|
|
// The EFLAGS implicit def is dead.
|
|
New->getOperand(3).setIsDead();
|
|
|
|
// Replace the pseudo instruction with a new instruction.
|
|
MBB.insert(I, New);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
|
|
// If we are performing frame pointer elimination and if the callee pops
|
|
// something off the stack pointer, add it back. We do this until we have
|
|
// more advanced stack pointer tracking ability.
|
|
unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
|
|
MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
|
|
.addReg(StackPtr).addImm(CalleeAmt);
|
|
|
|
// The EFLAGS implicit def is dead.
|
|
New->getOperand(3).setIsDead();
|
|
MBB.insert(I, New);
|
|
}
|
|
}
|
|
|
|
void
|
|
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const{
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
unsigned i = 0;
|
|
MachineInstr &MI = *II;
|
|
MachineFunction &MF = *MI.getParent()->getParent();
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
int FrameIndex = MI.getOperand(i).getIndex();
|
|
unsigned BasePtr;
|
|
|
|
unsigned Opc = MI.getOpcode();
|
|
bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
|
|
if (needsStackRealignment(MF))
|
|
BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
|
|
else if (AfterFPPop)
|
|
BasePtr = StackPtr;
|
|
else
|
|
BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
|
|
|
|
// This must be part of a four operand memory reference. Replace the
|
|
// FrameIndex with base register with EBP. Add an offset to the offset.
|
|
MI.getOperand(i).ChangeToRegister(BasePtr, false);
|
|
|
|
// Now add the frame object offset to the offset from EBP.
|
|
int FIOffset;
|
|
if (AfterFPPop) {
|
|
// Tail call jmp happens after FP is popped.
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
|
|
} else
|
|
FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
|
|
|
|
if (MI.getOperand(i+3).isImm()) {
|
|
// Offset is a 32-bit integer.
|
|
int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
|
|
MI.getOperand(i + 3).ChangeToImmediate(Offset);
|
|
} else {
|
|
// Offset is symbolic. This is extremely rare.
|
|
uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
|
|
MI.getOperand(i+3).setOffset(Offset);
|
|
}
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getRARegister() const {
|
|
return Is64Bit ? X86::RIP // Should have dwarf #16.
|
|
: X86::EIP; // Should have dwarf #8.
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
return TFI->hasFP(MF) ? FramePtr : StackPtr;
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getEHExceptionRegister() const {
|
|
llvm_unreachable("What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getEHHandlerRegister() const {
|
|
llvm_unreachable("What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
namespace llvm {
|
|
unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
|
default: return Reg;
|
|
case MVT::i8:
|
|
if (High) {
|
|
switch (Reg) {
|
|
default: return 0;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AH;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DH;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CH;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BH;
|
|
}
|
|
} else {
|
|
switch (Reg) {
|
|
default: return 0;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AL;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DL;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CL;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BL;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SIL;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DIL;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BPL;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SPL;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8B;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9B;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10B;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11B;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12B;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13B;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14B;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15B;
|
|
}
|
|
}
|
|
case MVT::i16:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8W;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9W;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10W;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11W;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12W;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13W;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14W;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15W;
|
|
}
|
|
case MVT::i32:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::EAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::EDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::ECX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::EBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::ESI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::EDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::EBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::ESP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8D;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9D;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10D;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11D;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12D;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13D;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14D;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15D;
|
|
}
|
|
case MVT::i64:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::RAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::RDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::RCX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::RBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::RSI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::RDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::RBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::RSP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15;
|
|
}
|
|
}
|
|
|
|
return Reg;
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
struct MSAH : public MachineFunctionPass {
|
|
static char ID;
|
|
MSAH() : MachineFunctionPass(ID) {}
|
|
|
|
virtual bool runOnMachineFunction(MachineFunction &MF) {
|
|
const X86TargetMachine *TM =
|
|
static_cast<const X86TargetMachine *>(&MF.getTarget());
|
|
const TargetFrameLowering *TFI = TM->getFrameLowering();
|
|
MachineRegisterInfo &RI = MF.getRegInfo();
|
|
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
|
|
unsigned StackAlignment = TFI->getStackAlignment();
|
|
|
|
// Be over-conservative: scan over all vreg defs and find whether vector
|
|
// registers are used. If yes, there is a possibility that vector register
|
|
// will be spilled and thus require dynamic stack realignment.
|
|
for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
|
|
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
|
|
if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
|
|
FuncInfo->setReserveFP(true);
|
|
return true;
|
|
}
|
|
}
|
|
// Nothing to do
|
|
return false;
|
|
}
|
|
|
|
virtual const char *getPassName() const {
|
|
return "X86 Maximal Stack Alignment Check";
|
|
}
|
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesCFG();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
};
|
|
|
|
char MSAH::ID = 0;
|
|
}
|
|
|
|
FunctionPass*
|
|
llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }
|