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https://github.com/c64scene-ar/llvm-6502.git
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3042a65e5f
logical operations on the i1's driving them. This is a bad idea for every target I can think of (confirmed with micro tests on all of: x86-64, ARM, AArch64, Mips, and PowerPC) because it forces the i1 to be materialized into a general purpose register, whereas consuming it directly into a select generally allows it to exist only transiently in a predicate or flags register. Chandler ran a set of performance tests with this change, and reported no measurable change on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201275 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
672 B
LLVM
25 lines
672 B
LLVM
; RUN: opt -instcombine -S < %s | FileCheck %s
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; CHECK: @foo1
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define float @foo1(float %a) #0 {
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; CHECK-NOT: xor
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%b = fcmp ogt float %a, 0.000000e+00
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%c = select i1 %b, float %a, float 0.000000e+00
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%d = fcmp olt float %c, 1.000000e+00
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%f = select i1 %d, float %c, float 1.000000e+00
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ret float %f
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}
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; CHECK: @foo2
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define float @foo2(float %a) #0 {
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; CHECK-NOT: xor
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%b = fcmp ogt float %a, 0.000000e+00
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%c = select i1 %b, float %a, float 0.000000e+00
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%d = fcmp olt float %c, 1.000000e+00
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%e = select i1 %b, float %a, float 0.000000e+00
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%f = select i1 %d, float %e, float 1.000000e+00
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ret float %f
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}
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attributes #0 = { nounwind readnone ssp uwtable }
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