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https://github.com/c64scene-ar/llvm-6502.git
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ebdeeab812
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.5 KiB
C++
47 lines
1.5 KiB
C++
//===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreMCAsmInfo.h"
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#include "XCoreTargetMachine.h"
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#include "XCore.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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/// XCoreTargetMachine ctor - Create an ILP32 architecture model
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///
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XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: LLVMTargetMachine(T, TT, CPU, FS),
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Subtarget(TT, CPU, FS),
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DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
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"i16:16:32-i32:32:32-i64:32:32-n32"),
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InstrInfo(),
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FrameLowering(Subtarget),
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TLInfo(*this),
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TSInfo(*this) {
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}
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bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createXCoreISelDag(*this));
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return false;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeXCoreTarget() {
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RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget);
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RegisterAsmInfo<XCoreMCAsmInfo> Y(TheXCoreTarget);
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}
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