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Fix a spello Tighten up the assertion checking No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11036 91177308-0d34-0410-b5e6-96231b3b80d8
163 lines
5.9 KiB
C++
163 lines
5.9 KiB
C++
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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// A = A op C
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//
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// Note that if a register allocator chooses to use this pass, that it has to
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// be capable of handling the non-SSA nature of these rewritten virtual
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// registers.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "Support/Debug.h"
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#include "Support/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<> numTwoAddressInstrs("twoaddressinstruction",
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"Number of two-address instructions");
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Statistic<> numInstrsAdded("twoaddressinstruction",
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"Number of instructions added");
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struct TwoAddressInstructionPass : public MachineFunctionPass
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{
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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};
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RegisterPass<TwoAddressInstructionPass> X(
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"twoaddressinstruction", "Two-Address instruction pass");
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};
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const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
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void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const
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{
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Reduce two-address instructions to two
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/// operands.
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(std::cerr << "Machine Function\n");
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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bool MadeChange = false;
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mii = mbbi->begin();
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mii != mbbi->end(); ++mii) {
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MachineInstr* mi = *mii;
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unsigned opcode = mi->getOpcode();
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// ignore if it is not a two-address instruction
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if (!TII.isTwoAddrInstr(opcode))
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continue;
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++numTwoAddressInstrs;
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DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
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assert(mi->getOperand(1).isRegister() &&
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mi->getOperand(1).getAllocatedRegNum() &&
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mi->getOperand(1).isUse() &&
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"two address instruction invalid");
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// we have nothing to do if the two operands are the same
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if (mi->getOperand(0).getAllocatedRegNum() ==
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mi->getOperand(1).getAllocatedRegNum())
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continue;
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MadeChange = true;
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(0).getAllocatedRegNum();
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unsigned regB = mi->getOperand(1).getAllocatedRegNum();
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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// first make sure we do not have a use of a in the
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// instruction (a = b + a for example) because our
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// transformation will not work. This should never occur
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// because we are in SSA form.
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for (unsigned i = 1; i != mi->getNumOperands(); ++i)
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assert(!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getAllocatedRegNum() != (int)regA);
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const TargetRegisterClass* rc =MF.getSSARegMap()->getRegClass(regA);
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unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
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numInstrsAdded += Added;
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MachineInstr* prevMi = *(mii - 1);
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DEBUG(std::cerr << "\t\tadded instruction: ";
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prevMi->print(std::cerr, TM));
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// update live variables for regA
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assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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varInfo.DefInst = prevMi;
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// update live variables for regB
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if (LV.removeVirtualRegisterKilled(regB, &*mbbi, mi))
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LV.addVirtualRegisterKilled(regB, &*mbbi, prevMi);
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if (LV.removeVirtualRegisterDead(regB, &*mbbi, mi))
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LV.addVirtualRegisterDead(regB, &*mbbi, prevMi);
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// replace all occurences of regB with regA
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for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->SetMachineOperandReg(i, regA);
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}
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DEBUG(std::cerr << "\t\tmodified original to: ";
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mi->print(std::cerr, TM));
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assert(mi->getOperand(0).getAllocatedRegNum() ==
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mi->getOperand(1).getAllocatedRegNum());
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}
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}
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return MadeChange;
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}
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