.. |
2r_vector_scalar.ll
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[mips][msa] Implemented fill.d intrinsic.
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2013-09-27 13:20:41 +00:00 |
2r.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
2rf_exup.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
2rf_float_int.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
2rf_fq.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
2rf_int_float.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
2rf_tq.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
2rf.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r_4r_widen.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r_4r.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r_ld_st.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r_splat.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-a.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-b.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-c.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-d.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-i.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-m.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-p.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-s.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3r-v.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf_4rf_q.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf_4rf.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf_exdo.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf_float_int.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf_int_float.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf_q.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
3rf.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
arithmetic_float.ll
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[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics)
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2013-10-11 10:27:32 +00:00 |
arithmetic.ll
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[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
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2013-10-01 10:22:35 +00:00 |
basic_operations_float.ll
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[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
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2013-09-27 12:31:32 +00:00 |
basic_operations.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
bit.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
bitcast.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
bitwise.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
compare_float.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
compare.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
elm_copy.ll
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[mips][msa] Implemented copy_[us].d intrinsic.
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2013-09-27 13:04:21 +00:00 |
elm_cxcmsa.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
elm_insv.ll
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[mips][msa] Implemented insert.d intrinsic.
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2013-09-27 13:36:54 +00:00 |
elm_move.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
elm_shift_slide.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i5_ld_st.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i5-a.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i5-b.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i5-c.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i5-m.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i5-s.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i8.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
i10.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
llvm-stress-s525530439.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
llvm-stress-s997348632.ll
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[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
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2013-09-27 12:17:32 +00:00 |
llvm-stress-s1935737938.ll
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[mips][msa] Added support for MSA registers to copyPhysReg
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2013-09-27 12:03:51 +00:00 |
llvm-stress-sz1-s742806235.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
shuffle.ll
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[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
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2013-09-27 11:48:57 +00:00 |
spill.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
vec.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |
vecs10.ll
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
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2013-09-27 10:08:31 +00:00 |