mirror of
https://github.com/c64scene-ar/llvm-6502.git
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24e79e55da
Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
420 lines
12 KiB
TableGen
420 lines
12 KiB
TableGen
//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips16 instructions.
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//
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//===----------------------------------------------------------------------===//
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//
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// RRR-type instruction format
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//
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class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
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//
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// I8_MOV32R instruction format (used only by MOV32R instruction)
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//
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class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
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FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
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!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
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//
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// EXT-RI instruction format
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//
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class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
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!strconcat(asmstr, asmstr2), [], itin>;
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class FEXT_RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
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class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
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class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm"), [], itin> {
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let Constraints = "$rx_ = $rx";
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}
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//
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// RR-type instruction format
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//
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class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRxRxRy16_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $ry"),
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[], itin> {
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let Constraints = "$rx = $rz";
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}
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let rx=0 in
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class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
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[], itin> ;
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//
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// EXT-RRI instruction format
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//
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class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
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InstrItinClass itin>:
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FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
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!strconcat(asmstr, "\t$ry, $addr"), [], itin>;
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class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
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InstrItinClass itin>:
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FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
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!strconcat(asmstr, "\t$ry, $addr"), [], itin>;
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//
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// EXT-SHIFT instruction format
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//
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class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
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FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
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!strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
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//
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// Address operand
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def mem16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU16Regs, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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//
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// Some general instruction class info
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//
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//
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class ArithLogic16Defs<bit isCom=0> {
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bits<5> shamt = 0;
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bit isCommutable = isCom;
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bit isReMaterializable = 1;
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bit neverHasSideEffects = 1;
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}
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//
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// Format: ADDIU rx, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
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// To add a constant to a 32-bit integer.
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//
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def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
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def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
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ArithLogic16Defs<0>;
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//
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// Format: ADDIU rx, pc, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
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// To add a constant to the program counter.
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//
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def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
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//
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// Format: ADDU rz, rx, ry MIPS16e
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// Purpose: Add Unsigned Word (3-Operand)
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// To add 32-bit integers.
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//
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def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
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//
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// Format: AND rx, ry MIPS16e
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// Purpose: AND
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// To do a bitwise logical AND.
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def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
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//
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// Format: JR ra MIPS16e
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// Purpose: Jump Register Through Register ra
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// To execute a branch to the instruction address in the return
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// address register.
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//
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def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>;
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//
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// Format: LB ry, offset(rx) MIPS16e
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// Purpose: Load Byte (Extended)
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// To load a byte from memory as a signed value.
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//
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def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IIAlu>;
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//
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// Format: LBU ry, offset(rx) MIPS16e
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// Purpose: Load Byte Unsigned (Extended)
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// To load a byte from memory as a unsigned value.
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//
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def LbuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IIAlu>;
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//
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// Format: LH ry, offset(rx) MIPS16e
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// Purpose: Load Halfword signed (Extended)
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// To load a halfword from memory as a signed value.
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//
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def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IIAlu>;
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//
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// Format: LHU ry, offset(rx) MIPS16e
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// Purpose: Load Halfword unsigned (Extended)
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// To load a halfword from memory as an unsigned value.
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//
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def LhuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IIAlu>;
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//
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// Format: LI rx, immediate MIPS16e
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// Purpose: Load Immediate (Extended)
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// To load a constant into a GPR.
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//
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def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
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//
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// Format: LW ry, offset(rx) MIPS16e
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// Purpose: Load Word (Extended)
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// To load a word from memory as a signed value.
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//
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def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>;
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//
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// Format: MOVE r32, rz MIPS16e
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// Purpose: Move
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// To move the contents of a GPR to a GPR.
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//
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def Mov32R16: FI8_MOV32R16_ins<"move", IIAlu>;
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//
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// Format: NEG rx, ry MIPS16e
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// Purpose: Negate
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// To negate an integer value.
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//
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def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>;
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//
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// Format: NOT rx, ry MIPS16e
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// Purpose: Not
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// To complement an integer value
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//
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def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>;
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//
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// Format: OR rx, ry MIPS16e
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// Purpose: Or
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// To do a bitwise logical OR.
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//
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def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
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//
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// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
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// (All args are optional) MIPS16e
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// Purpose: Restore Registers and Deallocate Stack Frame
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// To deallocate a stack frame before exit from a subroutine,
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// restoring return address and static registers, and adjusting
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// stack
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//
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// fixed form for restoring RA and the frame
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// for direct object emitter, encoding needs to be adjusted for the
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// frame size
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//
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let ra=1, s=0,s0=0,s1=0 in
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def RestoreRaF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"restore \t$$ra, $frame_size", [], IILoad >;
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//
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// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
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// MIPS16e
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// Purpose: Save Registers and Set Up Stack Frame
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// To set up a stack frame on entry to a subroutine,
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// saving return address and static registers, and adjusting stack
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//
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let ra=1, s=1,s0=0,s1=0 in
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def SaveRaF16:
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FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
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"save \t$$ra, $frame_size", [], IILoad >;
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//
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// Format: SB ry, offset(rx) MIPS16e
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// Purpose: Store Byte (Extended)
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// To store a byte to memory.
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//
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def SbRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIAlu>;
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//
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// Format: SH ry, offset(rx) MIPS16e
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// Purpose: Store Halfword (Extended)
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// To store a halfword to memory.
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//
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def ShRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIAlu>;
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//
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// Format: SLL rx, ry, sa MIPS16e
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// Purpose: Shift Word Left Logical (Extended)
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// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
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//
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def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
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//
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// Format: SLLV ry, rx MIPS16e
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// Purpose: Shift Word Left Logical Variable
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// To execute a left-shift of a word by a variable number of bits.
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//
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def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
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//
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// Format: SRAV ry, rx MIPS16e
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// Purpose: Shift Word Right Arithmetic Variable
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// To execute an arithmetic right-shift of a word by a variable
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// number of bits.
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//
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def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
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//
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// Format: SRA rx, ry, sa MIPS16e
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// Purpose: Shift Word Right Arithmetic (Extended)
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// To execute an arithmetic right-shift of a word by a fixed
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// number of bits—1 to 8 bits.
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//
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def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
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//
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// Format: SRLV ry, rx MIPS16e
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// Purpose: Shift Word Right Logical Variable
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// To execute a logical right-shift of a word by a variable
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// number of bits.
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//
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def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
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//
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// Format: SRL rx, ry, sa MIPS16e
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// Purpose: Shift Word Right Logical (Extended)
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// To execute a logical right-shift of a word by a fixed
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// number of bits—1 to 31 bits.
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//
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def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
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//
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// Format: SUBU rz, rx, ry MIPS16e
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// Purpose: Subtract Unsigned Word
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// To subtract 32-bit integers
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//
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def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
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//
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// Format: SW ry, offset(rx) MIPS16e
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// Purpose: Store Word (Extended)
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// To store a word to memory.
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//
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def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIAlu>;
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//
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// Format: XOR rx, ry MIPS16e
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// Purpose: Xor
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// To do a bitwise logical XOR.
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//
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def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
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class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
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let Predicates = [InMips16Mode];
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}
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// Unary Arith/Logic
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//
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class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
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Mips16Pat<(OpNode CPU16Regs:$r),
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(I CPU16Regs:$r)>;
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def: ArithLogicU_pat<not, NotRxRy16>;
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def: ArithLogicU_pat<ineg, NegRxRy16>;
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class ArithLogic16_pat<SDNode OpNode, Instruction I> :
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Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
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(I CPU16Regs:$l, CPU16Regs:$r)>;
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def: ArithLogic16_pat<add, AdduRxRyRz16>;
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def: ArithLogic16_pat<and, AndRxRxRy16>;
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def: ArithLogic16_pat<or, OrRxRxRy16>;
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def: ArithLogic16_pat<sub, SubuRxRyRz16>;
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def: ArithLogic16_pat<xor, XorRxRxRy16>;
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// Arithmetic and logical instructions with 2 register operands.
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class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
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Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
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(I CPU16Regs:$in, imm_type:$imm)>;
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def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
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def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
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def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
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def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
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class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
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Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
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(I CPU16Regs:$r, CPU16Regs:$ra)>;
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def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
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def: shift_rotate_reg16_pat<sra, SravRxRy16>;
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def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
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class LoadM16_pat<PatFrag OpNode, Instruction I> :
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Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>;
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def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
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def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
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def: LoadM16_pat<sextloadi16_a, LhRxRyOffMemX16>;
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def: LoadM16_pat<zextloadi16_a, LhuRxRyOffMemX16>;
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def: LoadM16_pat<load_a, LwRxRyOffMemX16>;
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class StoreM16_pat<PatFrag OpNode, Instruction I> :
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Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>;
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def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
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def: StoreM16_pat<truncstorei16_a, ShRxRyOffMemX16>;
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def: StoreM16_pat<store_a, SwRxRyOffMemX16>;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1 in
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def JumpLinkReg16:
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FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
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"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
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// Mips16 pseudos
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
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hasExtraSrcRegAllocReq = 1 in
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def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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// Small immediates
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def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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