mirror of
https://github.com/c64scene-ar/llvm-6502.git
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87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
6.9 KiB
C++
202 lines
6.9 KiB
C++
//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides AArch64 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64MCTargetDesc.h"
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#include "AArch64ELFStreamer.h"
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#include "AArch64MCAsmInfo.h"
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#include "InstPrinter/AArch64InstPrinter.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_MC_DESC
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#include "AArch64GenRegisterInfo.inc"
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#define GET_INSTRINFO_MC_DESC
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#include "AArch64GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AArch64GenSubtargetInfo.inc"
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using namespace llvm;
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MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT,
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StringRef CPU,
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StringRef FS) {
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCInstrInfo *createAArch64MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitAArch64MCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitAArch64MCRegisterInfo(X, AArch64::X30);
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return X;
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}
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static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
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StringRef TT) {
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Triple TheTriple(TT);
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MCAsmInfo *MAI = new AArch64ELFMCAsmInfo();
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unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC) {
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// On ELF platforms the default static relocation model has a smart enough
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// linker to cope with referencing external symbols defined in a shared
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// library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
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RM = Reloc::Static;
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}
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if (CM == CodeModel::Default)
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CM = CodeModel::Small;
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else if (CM == CodeModel::JITDefault) {
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// The default MCJIT memory managers make no guarantees about where they can
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// find an executable page; JITed code needs to be able to refer to globals
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// no matter how far away they are.
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CM = CodeModel::Large;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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bool RelaxAll,
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bool NoExecStack) {
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Triple TheTriple(TT);
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return createAArch64ELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
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}
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static MCInstPrinter *createAArch64MCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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if (SyntaxVariant == 0)
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return new AArch64InstPrinter(MAI, MII, MRI, STI);
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return 0;
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}
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namespace {
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class AArch64MCInstrAnalysis : public MCInstrAnalysis {
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public:
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AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
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virtual bool isUnconditionalBranch(const MCInst &Inst) const {
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if (Inst.getOpcode() == AArch64::Bcc
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&& Inst.getOperand(0).getImm() == A64CC::AL)
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return true;
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return MCInstrAnalysis::isUnconditionalBranch(Inst);
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}
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virtual bool isConditionalBranch(const MCInst &Inst) const {
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if (Inst.getOpcode() == AArch64::Bcc
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&& Inst.getOperand(0).getImm() == A64CC::AL)
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return false;
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return MCInstrAnalysis::isConditionalBranch(Inst);
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}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
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// FIXME: We only handle PCRel branches for now.
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if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
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!= MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(LblOperand).getImm();
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Target = Addr + Imm;
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return true;
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}
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};
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}
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static MCInstrAnalysis *createAArch64MCInstrAnalysis(const MCInstrInfo *Info) {
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return new AArch64MCInstrAnalysis(Info);
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}
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extern "C" void LLVMInitializeAArch64TargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn A(TheAArch64Target, createAArch64MCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheAArch64Target,
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createAArch64MCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheAArch64Target,
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createAArch64MCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheAArch64Target,
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createAArch64MCRegisterInfo);
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// Register the MC subtarget info.
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using AArch64_MC::createAArch64MCSubtargetInfo;
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TargetRegistry::RegisterMCSubtargetInfo(TheAArch64Target,
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createAArch64MCSubtargetInfo);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(TheAArch64Target,
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createAArch64MCInstrAnalysis);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheAArch64Target,
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createAArch64MCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheAArch64Target,
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createAArch64AsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterMCObjectStreamer(TheAArch64Target,
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createMCStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheAArch64Target,
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createAArch64MCInstPrinter);
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}
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