mirror of
https://github.com/c64scene-ar/llvm-6502.git
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27b1252c13
This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
276 lines
7.6 KiB
LLVM
276 lines
7.6 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vaddi8:
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;CHECK: vadd.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = add <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vaddi16:
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;CHECK: vadd.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = add <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vaddi32:
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;CHECK: vadd.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = add <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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;CHECK-LABEL: vaddi64:
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;CHECK: vadd.i64
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = add <1 x i64> %tmp1, %tmp2
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ret <1 x i64> %tmp3
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}
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define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vaddf32:
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;CHECK: vadd.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fadd <2 x float> %tmp1, %tmp2
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ret <2 x float> %tmp3
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}
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define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vaddQi8:
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;CHECK: vadd.i8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = add <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vaddQi16:
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;CHECK: vadd.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = add <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vaddQi32:
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;CHECK: vadd.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = add <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vaddQi64:
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;CHECK: vadd.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = add <2 x i64> %tmp1, %tmp2
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ret <2 x i64> %tmp3
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}
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define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vaddQf32:
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;CHECK: vadd.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = fadd <4 x float> %tmp1, %tmp2
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ret <4 x float> %tmp3
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}
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define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vraddhni16:
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;CHECK: vraddhn.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vraddhni32:
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;CHECK: vraddhn.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vraddhni64:
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;CHECK: vraddhn.i64
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind {
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; CHECK-LABEL: vaddhni16_natural:
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; CHECK: vaddhn.i16
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%sum = add <8 x i16> %A, %B
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%shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%trunc = trunc <8 x i16> %shift to <8 x i8>
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ret <8 x i8> %trunc
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}
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define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind {
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; CHECK-LABEL: vaddhni32_natural:
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; CHECK: vaddhn.i32
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%sum = add <4 x i32> %A, %B
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%shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
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%trunc = trunc <4 x i32> %shift to <4 x i16>
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ret <4 x i16> %trunc
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}
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define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK-LABEL: vaddhni64_natural:
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; CHECK: vaddhn.i64
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%sum = add <2 x i64> %A, %B
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%shift = lshr <2 x i64> %sum, <i64 32, i64 32>
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%trunc = trunc <2 x i64> %shift to <2 x i32>
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ret <2 x i32> %trunc
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}
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define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vaddls8:
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;CHECK: vaddl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
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%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vaddls16:
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;CHECK: vaddl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
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%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vaddls32:
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;CHECK: vaddl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
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%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
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%tmp5 = add <2 x i64> %tmp3, %tmp4
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ret <2 x i64> %tmp5
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}
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define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vaddlu8:
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;CHECK: vaddl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
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%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vaddlu16:
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;CHECK: vaddl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
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%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vaddlu32:
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;CHECK: vaddl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
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%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
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%tmp5 = add <2 x i64> %tmp3, %tmp4
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ret <2 x i64> %tmp5
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}
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define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vaddws8:
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;CHECK: vaddw.s8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vaddws16:
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;CHECK: vaddw.s16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vaddws32:
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;CHECK: vaddw.s32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vaddwu8:
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;CHECK: vaddw.u8
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vaddwu16:
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;CHECK: vaddw.u16
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vaddwu32:
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;CHECK: vaddw.u32
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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