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bb5b3f3359
promoting allocas to preferred alignments that exceed the natural alignment. This avoids some potentially expensive dynamic stack realignments. The natural stack alignment is set in target data strings via the "S<size>" option. Size is in bits and must be a multiple of 8. The natural stack alignment defaults to "unspecified" (represented by a zero value), and the "unspecified" value does not prevent any alignment promotions. Target maintainers that care about avoiding promotions should explicitly add the "S<size>" option to their target data strings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
938 lines
26 KiB
Plaintext
938 lines
26 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend: SSE-specific stuff.
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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SSE Variable shift can be custom lowered to something like this, which uses a
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small table + unaligned load + shuffle instead of going through memory.
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__m128i_shift_right:
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.byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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.byte -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
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...
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__m128i shift_right(__m128i value, unsigned long offset) {
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return _mm_shuffle_epi8(value,
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_mm_loadu_si128((__m128 *) (___m128i_shift_right + offset)));
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}
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//===---------------------------------------------------------------------===//
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SSE has instructions for doing operations on complex numbers, we should pattern
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match them. For example, this should turn into a horizontal add:
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typedef float __attribute__((vector_size(16))) v4f32;
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float f32(v4f32 A) {
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return A[0]+A[1]+A[2]+A[3];
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}
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Instead we get this:
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_f32: ## @f32
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pshufd $1, %xmm0, %xmm1 ## xmm1 = xmm0[1,0,0,0]
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addss %xmm0, %xmm1
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pshufd $3, %xmm0, %xmm2 ## xmm2 = xmm0[3,0,0,0]
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movhlps %xmm0, %xmm0 ## xmm0 = xmm0[1,1]
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movaps %xmm0, %xmm3
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addss %xmm1, %xmm3
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movdqa %xmm2, %xmm0
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addss %xmm3, %xmm0
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ret
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Also, there are cases where some simple local SLP would improve codegen a bit.
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compiling this:
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_Complex float f32(_Complex float A, _Complex float B) {
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return A+B;
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}
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into:
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_f32: ## @f32
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movdqa %xmm0, %xmm2
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addss %xmm1, %xmm2
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pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
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pshufd $1, %xmm0, %xmm3 ## xmm3 = xmm0[1,0,0,0]
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addss %xmm1, %xmm3
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movaps %xmm2, %xmm0
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unpcklps %xmm3, %xmm0 ## xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
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ret
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seems silly when it could just be one addps.
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//===---------------------------------------------------------------------===//
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Expand libm rounding functions inline: Significant speedups possible.
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http://gcc.gnu.org/ml/gcc-patches/2006-10/msg00909.html
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//===---------------------------------------------------------------------===//
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When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and
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other fast SSE modes.
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//===---------------------------------------------------------------------===//
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Think about doing i64 math in SSE regs on x86-32.
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//===---------------------------------------------------------------------===//
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This testcase should have no SSE instructions in it, and only one load from
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a constant pool:
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double %test3(bool %B) {
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%C = select bool %B, double 123.412, double 523.01123123
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ret double %C
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}
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Currently, the select is being lowered, which prevents the dag combiner from
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turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)'
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The pattern isel got this one right.
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//===---------------------------------------------------------------------===//
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SSE should implement 'select_cc' using 'emulated conditional moves' that use
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pcmp/pand/pandn/por to do a selection instead of a conditional branch:
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double %X(double %Y, double %Z, double %A, double %B) {
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%C = setlt double %A, %B
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%z = fadd double %Z, 0.0 ;; select operand is not a load
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%D = select bool %C, double %Y, double %z
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ret double %D
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}
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We currently emit:
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_X:
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subl $12, %esp
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xorpd %xmm0, %xmm0
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addsd 24(%esp), %xmm0
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movsd 32(%esp), %xmm1
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movsd 16(%esp), %xmm2
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ucomisd 40(%esp), %xmm1
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jb LBB_X_2
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LBB_X_1:
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movsd %xmm0, %xmm2
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LBB_X_2:
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movsd %xmm2, (%esp)
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fldl (%esp)
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addl $12, %esp
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ret
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//===---------------------------------------------------------------------===//
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Lower memcpy / memset to a series of SSE 128 bit move instructions when it's
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feasible.
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//===---------------------------------------------------------------------===//
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Codegen:
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if (copysign(1.0, x) == copysign(1.0, y))
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into:
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if (x^y & mask)
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when using SSE.
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//===---------------------------------------------------------------------===//
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Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half
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of a v4sf value.
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//===---------------------------------------------------------------------===//
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Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}.
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Perhaps use pxor / xorp* to clear a XMM register first?
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//===---------------------------------------------------------------------===//
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External test Nurbs exposed some problems. Look for
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__ZN15Nurbs_SSE_Cubic17TessellateSurfaceE, bb cond_next140. This is what icc
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emits:
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movaps (%edx), %xmm2 #59.21
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movaps (%edx), %xmm5 #60.21
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movaps (%edx), %xmm4 #61.21
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movaps (%edx), %xmm3 #62.21
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movl 40(%ecx), %ebp #69.49
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shufps $0, %xmm2, %xmm5 #60.21
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movl 100(%esp), %ebx #69.20
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movl (%ebx), %edi #69.20
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imull %ebp, %edi #69.49
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addl (%eax), %edi #70.33
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shufps $85, %xmm2, %xmm4 #61.21
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shufps $170, %xmm2, %xmm3 #62.21
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shufps $255, %xmm2, %xmm2 #63.21
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lea (%ebp,%ebp,2), %ebx #69.49
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negl %ebx #69.49
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lea -3(%edi,%ebx), %ebx #70.33
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shll $4, %ebx #68.37
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addl 32(%ecx), %ebx #68.37
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testb $15, %bl #91.13
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jne L_B1.24 # Prob 5% #91.13
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This is the llvm code after instruction scheduling:
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cond_next140 (0xa910740, LLVM BB @0xa90beb0):
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%reg1078 = MOV32ri -3
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%reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0
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%reg1037 = MOV32rm %reg1024, 1, %NOREG, 40
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%reg1080 = IMUL32rr %reg1079, %reg1037
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%reg1081 = MOV32rm %reg1058, 1, %NOREG, 0
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%reg1038 = LEA32r %reg1081, 1, %reg1080, -3
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%reg1036 = MOV32rm %reg1024, 1, %NOREG, 32
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%reg1082 = SHL32ri %reg1038, 4
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%reg1039 = ADD32rr %reg1036, %reg1082
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%reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0
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%reg1034 = SHUFPSrr %reg1083, %reg1083, 170
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%reg1032 = SHUFPSrr %reg1083, %reg1083, 0
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%reg1035 = SHUFPSrr %reg1083, %reg1083, 255
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%reg1033 = SHUFPSrr %reg1083, %reg1083, 85
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%reg1040 = MOV32rr %reg1039
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%reg1084 = AND32ri8 %reg1039, 15
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CMP32ri8 %reg1084, 0
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JE mbb<cond_next204,0xa914d30>
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Still ok. After register allocation:
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cond_next140 (0xa910740, LLVM BB @0xa90beb0):
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%EAX = MOV32ri -3
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%EDX = MOV32rm <fi#3>, 1, %NOREG, 0
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ADD32rm %EAX<def&use>, %EDX, 1, %NOREG, 0
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%EDX = MOV32rm <fi#7>, 1, %NOREG, 0
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%EDX = MOV32rm %EDX, 1, %NOREG, 40
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IMUL32rr %EAX<def&use>, %EDX
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%ESI = MOV32rm <fi#5>, 1, %NOREG, 0
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%ESI = MOV32rm %ESI, 1, %NOREG, 0
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MOV32mr <fi#4>, 1, %NOREG, 0, %ESI
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%EAX = LEA32r %ESI, 1, %EAX, -3
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%ESI = MOV32rm <fi#7>, 1, %NOREG, 0
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%ESI = MOV32rm %ESI, 1, %NOREG, 32
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%EDI = MOV32rr %EAX
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SHL32ri %EDI<def&use>, 4
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ADD32rr %EDI<def&use>, %ESI
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%XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0
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%XMM1 = MOVAPSrr %XMM0
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SHUFPSrr %XMM1<def&use>, %XMM1, 170
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%XMM2 = MOVAPSrr %XMM0
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SHUFPSrr %XMM2<def&use>, %XMM2, 0
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%XMM3 = MOVAPSrr %XMM0
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SHUFPSrr %XMM3<def&use>, %XMM3, 255
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SHUFPSrr %XMM0<def&use>, %XMM0, 85
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%EBX = MOV32rr %EDI
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AND32ri8 %EBX<def&use>, 15
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CMP32ri8 %EBX, 0
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JE mbb<cond_next204,0xa914d30>
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This looks really bad. The problem is shufps is a destructive opcode. Since it
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appears as operand two in more than one shufps ops. It resulted in a number of
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copies. Note icc also suffers from the same problem. Either the instruction
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selector should select pshufd or The register allocator can made the two-address
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to three-address transformation.
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It also exposes some other problems. See MOV32ri -3 and the spills.
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//===---------------------------------------------------------------------===//
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Consider:
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__m128 test(float a) {
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return _mm_set_ps(0.0, 0.0, 0.0, a*a);
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}
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This compiles into:
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movss 4(%esp), %xmm1
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mulss %xmm1, %xmm1
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xorps %xmm0, %xmm0
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movss %xmm1, %xmm0
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ret
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Because mulss doesn't modify the top 3 elements, the top elements of
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xmm1 are already zero'd. We could compile this to:
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movss 4(%esp), %xmm0
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mulss %xmm0, %xmm0
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ret
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//===---------------------------------------------------------------------===//
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Here's a sick and twisted idea. Consider code like this:
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__m128 test(__m128 a) {
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float b = *(float*)&A;
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...
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return _mm_set_ps(0.0, 0.0, 0.0, b);
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}
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This might compile to this code:
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movaps c(%esp), %xmm1
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xorps %xmm0, %xmm0
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movss %xmm1, %xmm0
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ret
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Now consider if the ... code caused xmm1 to get spilled. This might produce
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this code:
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movaps c(%esp), %xmm1
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movaps %xmm1, c2(%esp)
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...
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xorps %xmm0, %xmm0
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movaps c2(%esp), %xmm1
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movss %xmm1, %xmm0
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ret
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However, since the reload is only used by these instructions, we could
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"fold" it into the uses, producing something like this:
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movaps c(%esp), %xmm1
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movaps %xmm1, c2(%esp)
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...
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movss c2(%esp), %xmm0
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ret
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... saving two instructions.
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The basic idea is that a reload from a spill slot, can, if only one 4-byte
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chunk is used, bring in 3 zeros the one element instead of 4 elements.
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This can be used to simplify a variety of shuffle operations, where the
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elements are fixed zeros.
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//===---------------------------------------------------------------------===//
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This code generates ugly code, probably due to costs being off or something:
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define void @test(float* %P, <4 x float>* %P2 ) {
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%xFloat0.688 = load float* %P
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%tmp = load <4 x float>* %P2
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%inFloat3.713 = insertelement <4 x float> %tmp, float 0.0, i32 3
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store <4 x float> %inFloat3.713, <4 x float>* %P2
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ret void
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}
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Generates:
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_test:
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movl 8(%esp), %eax
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movaps (%eax), %xmm0
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pxor %xmm1, %xmm1
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movaps %xmm0, %xmm2
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shufps $50, %xmm1, %xmm2
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shufps $132, %xmm2, %xmm0
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movaps %xmm0, (%eax)
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ret
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Would it be better to generate:
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_test:
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movl 8(%esp), %ecx
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movaps (%ecx), %xmm0
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xor %eax, %eax
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pinsrw $6, %eax, %xmm0
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pinsrw $7, %eax, %xmm0
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movaps %xmm0, (%ecx)
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ret
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?
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//===---------------------------------------------------------------------===//
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Some useful information in the Apple Altivec / SSE Migration Guide:
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http://developer.apple.com/documentation/Performance/Conceptual/
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Accelerate_sse_migration/index.html
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e.g. SSE select using and, andnot, or. Various SSE compare translations.
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//===---------------------------------------------------------------------===//
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Add hooks to commute some CMPP operations.
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//===---------------------------------------------------------------------===//
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Apply the same transformation that merged four float into a single 128-bit load
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to loads from constant pool.
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//===---------------------------------------------------------------------===//
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Floating point max / min are commutable when -enable-unsafe-fp-path is
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specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
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nodes which are selected to max / min instructions that are marked commutable.
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//===---------------------------------------------------------------------===//
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We should materialize vector constants like "all ones" and "signbit" with
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code like:
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cmpeqps xmm1, xmm1 ; xmm1 = all-ones
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and:
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cmpeqps xmm1, xmm1 ; xmm1 = all-ones
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psrlq xmm1, 31 ; xmm1 = all 100000000000...
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instead of using a load from the constant pool. The later is important for
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ABS/NEG/copysign etc.
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//===---------------------------------------------------------------------===//
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These functions:
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#include <xmmintrin.h>
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__m128i a;
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void x(unsigned short n) {
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a = _mm_slli_epi32 (a, n);
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}
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void y(unsigned n) {
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a = _mm_slli_epi32 (a, n);
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}
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compile to ( -O3 -static -fomit-frame-pointer):
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_x:
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movzwl 4(%esp), %eax
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movd %eax, %xmm0
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movaps _a, %xmm1
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pslld %xmm0, %xmm1
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movaps %xmm1, _a
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ret
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_y:
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movd 4(%esp), %xmm0
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movaps _a, %xmm1
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pslld %xmm0, %xmm1
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movaps %xmm1, _a
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ret
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"y" looks good, but "x" does silly movzwl stuff around into a GPR. It seems
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like movd would be sufficient in both cases as the value is already zero
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extended in the 32-bit stack slot IIRC. For signed short, it should also be
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save, as a really-signed value would be undefined for pslld.
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//===---------------------------------------------------------------------===//
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#include <math.h>
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int t1(double d) { return signbit(d); }
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This currently compiles to:
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subl $12, %esp
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movsd 16(%esp), %xmm0
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movsd %xmm0, (%esp)
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movl 4(%esp), %eax
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shrl $31, %eax
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addl $12, %esp
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ret
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We should use movmskp{s|d} instead.
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//===---------------------------------------------------------------------===//
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CodeGen/X86/vec_align.ll tests whether we can turn 4 scalar loads into a single
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(aligned) vector load. This functionality has a couple of problems.
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1. The code to infer alignment from loads of globals is in the X86 backend,
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not the dag combiner. This is because dagcombine2 needs to be able to see
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through the X86ISD::Wrapper node, which DAGCombine can't really do.
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2. The code for turning 4 x load into a single vector load is target
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independent and should be moved to the dag combiner.
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3. The code for turning 4 x load into a vector load can only handle a direct
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load from a global or a direct load from the stack. It should be generalized
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to handle any load from P, P+4, P+8, P+12, where P can be anything.
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4. The alignment inference code cannot handle loads from globals in non-static
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mode because it doesn't look through the extra dyld stub load. If you try
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vec_align.ll without -relocation-model=static, you'll see what I mean.
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//===---------------------------------------------------------------------===//
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We should lower store(fneg(load p), q) into an integer load+xor+store, which
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eliminates a constant pool load. For example, consider:
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define i64 @ccosf(float %z.0, float %z.1) nounwind readonly {
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entry:
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%tmp6 = fsub float -0.000000e+00, %z.1 ; <float> [#uses=1]
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%tmp20 = tail call i64 @ccoshf( float %tmp6, float %z.0 ) nounwind readonly
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ret i64 %tmp20
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}
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declare i64 @ccoshf(float %z.0, float %z.1) nounwind readonly
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This currently compiles to:
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LCPI1_0: # <4 x float>
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.long 2147483648 # float -0
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.long 2147483648 # float -0
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.long 2147483648 # float -0
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.long 2147483648 # float -0
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_ccosf:
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subl $12, %esp
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movss 16(%esp), %xmm0
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movss %xmm0, 4(%esp)
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movss 20(%esp), %xmm0
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xorps LCPI1_0, %xmm0
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movss %xmm0, (%esp)
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call L_ccoshf$stub
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addl $12, %esp
|
|
ret
|
|
|
|
Note the load into xmm0, then xor (to negate), then store. In PIC mode,
|
|
this code computes the pic base and does two loads to do the constant pool
|
|
load, so the improvement is much bigger.
|
|
|
|
The tricky part about this xform is that the argument load/store isn't exposed
|
|
until post-legalize, and at that point, the fneg has been custom expanded into
|
|
an X86 fxor. This means that we need to handle this case in the x86 backend
|
|
instead of in target independent code.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Non-SSE4 insert into 16 x i8 is atrociously bad.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
<2 x i64> extract is substantially worse than <2 x f64>, even if the destination
|
|
is memory.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
SSE4 extract-to-mem ops aren't being pattern matched because of the AssertZext
|
|
sitting between the truncate and the extract.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
|
any number of 0.0 simultaneously. Currently we only use it for simple
|
|
insertions.
|
|
|
|
See comments in LowerINSERT_VECTOR_ELT_SSE4.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
On a random note, SSE2 should declare insert/extract of 2 x f64 as legal, not
|
|
Custom. All combinations of insert/extract reg-reg, reg-mem, and mem-reg are
|
|
legal, it'll just take a few extra patterns written in the .td file.
|
|
|
|
Note: this is not a code quality issue; the custom lowered code happens to be
|
|
right, but we shouldn't have to custom lower anything. This is probably related
|
|
to <2 x i64> ops being so bad.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
'select' on vectors and scalars could be a whole lot better. We currently
|
|
lower them to conditional branches. On x86-64 for example, we compile this:
|
|
|
|
double test(double a, double b, double c, double d) { return a<b ? c : d; }
|
|
|
|
to:
|
|
|
|
_test:
|
|
ucomisd %xmm0, %xmm1
|
|
ja LBB1_2 # entry
|
|
LBB1_1: # entry
|
|
movapd %xmm3, %xmm2
|
|
LBB1_2: # entry
|
|
movapd %xmm2, %xmm0
|
|
ret
|
|
|
|
instead of:
|
|
|
|
_test:
|
|
cmpltsd %xmm1, %xmm0
|
|
andpd %xmm0, %xmm2
|
|
andnpd %xmm3, %xmm0
|
|
orpd %xmm2, %xmm0
|
|
ret
|
|
|
|
For unpredictable branches, the later is much more efficient. This should
|
|
just be a matter of having scalar sse map to SELECT_CC and custom expanding
|
|
or iseling it.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
LLVM currently generates stack realignment code, when it is not necessary
|
|
needed. The problem is that we need to know about stack alignment too early,
|
|
before RA runs.
|
|
|
|
At that point we don't know, whether there will be vector spill, or not.
|
|
Stack realignment logic is overly conservative here, but otherwise we can
|
|
produce unaligned loads/stores.
|
|
|
|
Fixing this will require some huge RA changes.
|
|
|
|
Testcase:
|
|
#include <emmintrin.h>
|
|
|
|
typedef short vSInt16 __attribute__ ((__vector_size__ (16)));
|
|
|
|
static const vSInt16 a = {- 22725, - 12873, - 22725, - 12873, - 22725, - 12873,
|
|
- 22725, - 12873};;
|
|
|
|
vSInt16 madd(vSInt16 b)
|
|
{
|
|
return _mm_madd_epi16(a, b);
|
|
}
|
|
|
|
Generated code (x86-32, linux):
|
|
madd:
|
|
pushl %ebp
|
|
movl %esp, %ebp
|
|
andl $-16, %esp
|
|
movaps .LCPI1_0, %xmm1
|
|
pmaddwd %xmm1, %xmm0
|
|
movl %ebp, %esp
|
|
popl %ebp
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Consider:
|
|
#include <emmintrin.h>
|
|
__m128 foo2 (float x) {
|
|
return _mm_set_ps (0, 0, x, 0);
|
|
}
|
|
|
|
In x86-32 mode, we generate this spiffy code:
|
|
|
|
_foo2:
|
|
movss 4(%esp), %xmm0
|
|
pshufd $81, %xmm0, %xmm0
|
|
ret
|
|
|
|
in x86-64 mode, we generate this code, which could be better:
|
|
|
|
_foo2:
|
|
xorps %xmm1, %xmm1
|
|
movss %xmm0, %xmm1
|
|
pshufd $81, %xmm1, %xmm0
|
|
ret
|
|
|
|
In sse4 mode, we could use insertps to make both better.
|
|
|
|
Here's another testcase that could use insertps [mem]:
|
|
|
|
#include <xmmintrin.h>
|
|
extern float x2, x3;
|
|
__m128 foo1 (float x1, float x4) {
|
|
return _mm_set_ps (x2, x1, x3, x4);
|
|
}
|
|
|
|
gcc mainline compiles it to:
|
|
|
|
foo1:
|
|
insertps $0x10, x2(%rip), %xmm0
|
|
insertps $0x10, x3(%rip), %xmm1
|
|
movaps %xmm1, %xmm2
|
|
movlhps %xmm0, %xmm2
|
|
movaps %xmm2, %xmm0
|
|
ret
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We compile vector multiply-by-constant into poor code:
|
|
|
|
define <4 x i32> @f(<4 x i32> %i) nounwind {
|
|
%A = mul <4 x i32> %i, < i32 10, i32 10, i32 10, i32 10 >
|
|
ret <4 x i32> %A
|
|
}
|
|
|
|
On targets without SSE4.1, this compiles into:
|
|
|
|
LCPI1_0: ## <4 x i32>
|
|
.long 10
|
|
.long 10
|
|
.long 10
|
|
.long 10
|
|
.text
|
|
.align 4,0x90
|
|
.globl _f
|
|
_f:
|
|
pshufd $3, %xmm0, %xmm1
|
|
movd %xmm1, %eax
|
|
imull LCPI1_0+12, %eax
|
|
movd %eax, %xmm1
|
|
pshufd $1, %xmm0, %xmm2
|
|
movd %xmm2, %eax
|
|
imull LCPI1_0+4, %eax
|
|
movd %eax, %xmm2
|
|
punpckldq %xmm1, %xmm2
|
|
movd %xmm0, %eax
|
|
imull LCPI1_0, %eax
|
|
movd %eax, %xmm1
|
|
movhlps %xmm0, %xmm0
|
|
movd %xmm0, %eax
|
|
imull LCPI1_0+8, %eax
|
|
movd %eax, %xmm0
|
|
punpckldq %xmm0, %xmm1
|
|
movaps %xmm1, %xmm0
|
|
punpckldq %xmm2, %xmm0
|
|
ret
|
|
|
|
It would be better to synthesize integer vector multiplication by constants
|
|
using shifts and adds, pslld and paddd here. And even on targets with SSE4.1,
|
|
simple cases such as multiplication by powers of two would be better as
|
|
vector shifts than as multiplications.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We compile this:
|
|
|
|
__m128i
|
|
foo2 (char x)
|
|
{
|
|
return _mm_set_epi8 (1, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 1, 0, 0, 0, 0);
|
|
}
|
|
|
|
into:
|
|
movl $1, %eax
|
|
xorps %xmm0, %xmm0
|
|
pinsrw $2, %eax, %xmm0
|
|
movzbl 4(%esp), %eax
|
|
pinsrw $3, %eax, %xmm0
|
|
movl $256, %eax
|
|
pinsrw $7, %eax, %xmm0
|
|
ret
|
|
|
|
|
|
gcc-4.2:
|
|
subl $12, %esp
|
|
movzbl 16(%esp), %eax
|
|
movdqa LC0, %xmm0
|
|
pinsrw $3, %eax, %xmm0
|
|
addl $12, %esp
|
|
ret
|
|
.const
|
|
.align 4
|
|
LC0:
|
|
.word 0
|
|
.word 0
|
|
.word 1
|
|
.word 0
|
|
.word 0
|
|
.word 0
|
|
.word 0
|
|
.word 256
|
|
|
|
With SSE4, it should be
|
|
movdqa .LC0(%rip), %xmm0
|
|
pinsrb $6, %edi, %xmm0
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We should transform a shuffle of two vectors of constants into a single vector
|
|
of constants. Also, insertelement of a constant into a vector of constants
|
|
should also result in a vector of constants. e.g. 2008-06-25-VecISelBug.ll.
|
|
|
|
We compiled it to something horrible:
|
|
|
|
.align 4
|
|
LCPI1_1: ## float
|
|
.long 1065353216 ## float 1
|
|
.const
|
|
|
|
.align 4
|
|
LCPI1_0: ## <4 x float>
|
|
.space 4
|
|
.long 1065353216 ## float 1
|
|
.space 4
|
|
.long 1065353216 ## float 1
|
|
.text
|
|
.align 4,0x90
|
|
.globl _t
|
|
_t:
|
|
xorps %xmm0, %xmm0
|
|
movhps LCPI1_0, %xmm0
|
|
movss LCPI1_1, %xmm1
|
|
movaps %xmm0, %xmm2
|
|
shufps $2, %xmm1, %xmm2
|
|
shufps $132, %xmm2, %xmm0
|
|
movaps %xmm0, 0
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
rdar://5907648
|
|
|
|
This function:
|
|
|
|
float foo(unsigned char x) {
|
|
return x;
|
|
}
|
|
|
|
compiles to (x86-32):
|
|
|
|
define float @foo(i8 zeroext %x) nounwind {
|
|
%tmp12 = uitofp i8 %x to float ; <float> [#uses=1]
|
|
ret float %tmp12
|
|
}
|
|
|
|
compiles to:
|
|
|
|
_foo:
|
|
subl $4, %esp
|
|
movzbl 8(%esp), %eax
|
|
cvtsi2ss %eax, %xmm0
|
|
movss %xmm0, (%esp)
|
|
flds (%esp)
|
|
addl $4, %esp
|
|
ret
|
|
|
|
We should be able to use:
|
|
cvtsi2ss 8($esp), %xmm0
|
|
since we know the stack slot is already zext'd.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Consider using movlps instead of movsd to implement (scalar_to_vector (loadf64))
|
|
when code size is critical. movlps is slower than movsd on core2 but it's one
|
|
byte shorter.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
We should use a dynamic programming based approach to tell when using FPStack
|
|
operations is cheaper than SSE. SciMark montecarlo contains code like this
|
|
for example:
|
|
|
|
double MonteCarlo_num_flops(int Num_samples) {
|
|
return ((double) Num_samples)* 4.0;
|
|
}
|
|
|
|
In fpstack mode, this compiles into:
|
|
|
|
LCPI1_0:
|
|
.long 1082130432 ## float 4.000000e+00
|
|
_MonteCarlo_num_flops:
|
|
subl $4, %esp
|
|
movl 8(%esp), %eax
|
|
movl %eax, (%esp)
|
|
fildl (%esp)
|
|
fmuls LCPI1_0
|
|
addl $4, %esp
|
|
ret
|
|
|
|
in SSE mode, it compiles into significantly slower code:
|
|
|
|
_MonteCarlo_num_flops:
|
|
subl $12, %esp
|
|
cvtsi2sd 16(%esp), %xmm0
|
|
mulsd LCPI1_0, %xmm0
|
|
movsd %xmm0, (%esp)
|
|
fldl (%esp)
|
|
addl $12, %esp
|
|
ret
|
|
|
|
There are also other cases in scimark where using fpstack is better, it is
|
|
cheaper to do fld1 than load from a constant pool for example, so
|
|
"load, add 1.0, store" is better done in the fp stack, etc.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
The X86 backend should be able to if-convert SSE comparisons like "ucomisd" to
|
|
"cmpsd". For example, this code:
|
|
|
|
double d1(double x) { return x == x ? x : x + x; }
|
|
|
|
Compiles into:
|
|
|
|
_d1:
|
|
ucomisd %xmm0, %xmm0
|
|
jnp LBB1_2
|
|
addsd %xmm0, %xmm0
|
|
ret
|
|
LBB1_2:
|
|
ret
|
|
|
|
Also, the 'ret's should be shared. This is PR6032.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
These should compile into the same code (PR6214): Perhaps instcombine should
|
|
canonicalize the former into the later?
|
|
|
|
define float @foo(float %x) nounwind {
|
|
%t = bitcast float %x to i32
|
|
%s = and i32 %t, 2147483647
|
|
%d = bitcast i32 %s to float
|
|
ret float %d
|
|
}
|
|
|
|
declare float @fabsf(float %n)
|
|
define float @bar(float %x) nounwind {
|
|
%d = call float @fabsf(float %x)
|
|
ret float %d
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
This IR (from PR6194):
|
|
|
|
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
|
|
target triple = "x86_64-apple-darwin10.0.0"
|
|
|
|
%0 = type { double, double }
|
|
%struct.float3 = type { float, float, float }
|
|
|
|
define void @test(%0, %struct.float3* nocapture %res) nounwind noinline ssp {
|
|
entry:
|
|
%tmp18 = extractvalue %0 %0, 0 ; <double> [#uses=1]
|
|
%tmp19 = bitcast double %tmp18 to i64 ; <i64> [#uses=1]
|
|
%tmp20 = zext i64 %tmp19 to i128 ; <i128> [#uses=1]
|
|
%tmp10 = lshr i128 %tmp20, 32 ; <i128> [#uses=1]
|
|
%tmp11 = trunc i128 %tmp10 to i32 ; <i32> [#uses=1]
|
|
%tmp12 = bitcast i32 %tmp11 to float ; <float> [#uses=1]
|
|
%tmp5 = getelementptr inbounds %struct.float3* %res, i64 0, i32 1 ; <float*> [#uses=1]
|
|
store float %tmp12, float* %tmp5
|
|
ret void
|
|
}
|
|
|
|
Compiles to:
|
|
|
|
_test: ## @test
|
|
movd %xmm0, %rax
|
|
shrq $32, %rax
|
|
movl %eax, 4(%rdi)
|
|
ret
|
|
|
|
This would be better kept in the SSE unit by treating XMM0 as a 4xfloat and
|
|
doing a shuffle from v[1] to v[0] then a float store.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
On SSE4 machines, we compile this code:
|
|
|
|
define <2 x float> @test2(<2 x float> %Q, <2 x float> %R,
|
|
<2 x float> *%P) nounwind {
|
|
%Z = fadd <2 x float> %Q, %R
|
|
|
|
store <2 x float> %Z, <2 x float> *%P
|
|
ret <2 x float> %Z
|
|
}
|
|
|
|
into:
|
|
|
|
_test2: ## @test2
|
|
## BB#0:
|
|
insertps $0, %xmm2, %xmm2
|
|
insertps $16, %xmm3, %xmm2
|
|
insertps $0, %xmm0, %xmm3
|
|
insertps $16, %xmm1, %xmm3
|
|
addps %xmm2, %xmm3
|
|
movq %xmm3, (%rdi)
|
|
movaps %xmm3, %xmm0
|
|
pshufd $1, %xmm3, %xmm1
|
|
## kill: XMM1<def> XMM1<kill>
|
|
ret
|
|
|
|
The insertps's of $0 are pointless complex copies.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
If SSE4.1 is available we should inline rounding functions instead of emitting
|
|
a libcall.
|
|
|
|
floor: roundsd $0x01, %xmm, %xmm
|
|
ceil: roundsd $0x02, %xmm, %xmm
|
|
|
|
and likewise for the single precision versions.
|
|
|
|
Currently, SelectionDAGBuilder doesn't turn calls to these functions into the
|
|
corresponding nodes and some targets (including X86) aren't ready for them.
|
|
|
|
//===---------------------------------------------------------------------===//
|