mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-07 12:07:17 +00:00
928eb49cae
FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
5.7 KiB
TableGen
160 lines
5.7 KiB
TableGen
//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for ARM
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//
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def IIC_iALUx : InstrItinClass;
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def IIC_iALUi : InstrItinClass;
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def IIC_iALUr : InstrItinClass;
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def IIC_iALUsi : InstrItinClass;
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def IIC_iALUsr : InstrItinClass;
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def IIC_iUNAr : InstrItinClass;
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def IIC_iUNAsi : InstrItinClass;
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def IIC_iUNAsr : InstrItinClass;
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def IIC_iCMPi : InstrItinClass;
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def IIC_iCMPr : InstrItinClass;
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def IIC_iCMPsi : InstrItinClass;
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def IIC_iCMPsr : InstrItinClass;
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def IIC_iMOVi : InstrItinClass;
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def IIC_iMOVr : InstrItinClass;
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def IIC_iMOVsi : InstrItinClass;
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def IIC_iMOVsr : InstrItinClass;
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def IIC_iCMOVi : InstrItinClass;
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def IIC_iCMOVr : InstrItinClass;
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def IIC_iCMOVsi : InstrItinClass;
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def IIC_iCMOVsr : InstrItinClass;
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def IIC_iMUL16 : InstrItinClass;
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def IIC_iMAC16 : InstrItinClass;
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def IIC_iMUL32 : InstrItinClass;
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def IIC_iMAC32 : InstrItinClass;
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def IIC_iMUL64 : InstrItinClass;
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def IIC_iMAC64 : InstrItinClass;
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def IIC_iLoadi : InstrItinClass;
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def IIC_iLoadr : InstrItinClass;
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def IIC_iLoadsi : InstrItinClass;
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def IIC_iLoadiu : InstrItinClass;
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def IIC_iLoadru : InstrItinClass;
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def IIC_iLoadsiu : InstrItinClass;
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def IIC_iLoadm : InstrItinClass;
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def IIC_iStorei : InstrItinClass;
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def IIC_iStorer : InstrItinClass;
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def IIC_iStoresi : InstrItinClass;
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def IIC_iStoreiu : InstrItinClass;
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def IIC_iStoreru : InstrItinClass;
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def IIC_iStoresiu : InstrItinClass;
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def IIC_iStorem : InstrItinClass;
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def IIC_Br : InstrItinClass;
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def IIC_fpSTAT : InstrItinClass;
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def IIC_fpUNA32 : InstrItinClass;
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def IIC_fpUNA64 : InstrItinClass;
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def IIC_fpCMP32 : InstrItinClass;
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def IIC_fpCMP64 : InstrItinClass;
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def IIC_fpCVTSD : InstrItinClass;
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def IIC_fpCVTDS : InstrItinClass;
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def IIC_fpCVTSH : InstrItinClass;
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def IIC_fpCVTHS : InstrItinClass;
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def IIC_fpCVTIS : InstrItinClass;
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def IIC_fpCVTID : InstrItinClass;
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def IIC_fpCVTSI : InstrItinClass;
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def IIC_fpCVTDI : InstrItinClass;
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def IIC_fpMOVIS : InstrItinClass;
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def IIC_fpMOVID : InstrItinClass;
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def IIC_fpMOVSI : InstrItinClass;
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def IIC_fpMOVDI : InstrItinClass;
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def IIC_fpALU32 : InstrItinClass;
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def IIC_fpALU64 : InstrItinClass;
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def IIC_fpMUL32 : InstrItinClass;
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def IIC_fpMUL64 : InstrItinClass;
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def IIC_fpMAC32 : InstrItinClass;
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def IIC_fpMAC64 : InstrItinClass;
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def IIC_fpDIV32 : InstrItinClass;
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def IIC_fpDIV64 : InstrItinClass;
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def IIC_fpSQRT32 : InstrItinClass;
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def IIC_fpSQRT64 : InstrItinClass;
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def IIC_fpLoad32 : InstrItinClass;
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def IIC_fpLoad64 : InstrItinClass;
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def IIC_fpLoadm : InstrItinClass;
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def IIC_fpStore32 : InstrItinClass;
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def IIC_fpStore64 : InstrItinClass;
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def IIC_fpStorem : InstrItinClass;
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def IIC_VLD1 : InstrItinClass;
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def IIC_VLD2 : InstrItinClass;
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def IIC_VLD3 : InstrItinClass;
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def IIC_VLD4 : InstrItinClass;
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def IIC_VST : InstrItinClass;
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def IIC_VUNAD : InstrItinClass;
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def IIC_VUNAQ : InstrItinClass;
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def IIC_VBIND : InstrItinClass;
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def IIC_VBINQ : InstrItinClass;
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def IIC_VMOVImm : InstrItinClass;
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def IIC_VMOVD : InstrItinClass;
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def IIC_VMOVQ : InstrItinClass;
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def IIC_VMOVIS : InstrItinClass;
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def IIC_VMOVID : InstrItinClass;
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def IIC_VMOVISL : InstrItinClass;
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def IIC_VMOVSI : InstrItinClass;
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def IIC_VMOVDI : InstrItinClass;
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def IIC_VPERMD : InstrItinClass;
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def IIC_VPERMQ : InstrItinClass;
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def IIC_VPERMQ3 : InstrItinClass;
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def IIC_VMACD : InstrItinClass;
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def IIC_VMACQ : InstrItinClass;
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def IIC_VRECSD : InstrItinClass;
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def IIC_VRECSQ : InstrItinClass;
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def IIC_VCNTiD : InstrItinClass;
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def IIC_VCNTiQ : InstrItinClass;
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def IIC_VUNAiD : InstrItinClass;
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def IIC_VUNAiQ : InstrItinClass;
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def IIC_VQUNAiD : InstrItinClass;
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def IIC_VQUNAiQ : InstrItinClass;
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def IIC_VBINiD : InstrItinClass;
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def IIC_VBINiQ : InstrItinClass;
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def IIC_VSUBiD : InstrItinClass;
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def IIC_VSUBiQ : InstrItinClass;
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def IIC_VBINi4D : InstrItinClass;
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def IIC_VBINi4Q : InstrItinClass;
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def IIC_VSUBi4D : InstrItinClass;
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def IIC_VSUBi4Q : InstrItinClass;
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def IIC_VABAD : InstrItinClass;
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def IIC_VABAQ : InstrItinClass;
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def IIC_VSHLiD : InstrItinClass;
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def IIC_VSHLiQ : InstrItinClass;
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def IIC_VSHLi4D : InstrItinClass;
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def IIC_VSHLi4Q : InstrItinClass;
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def IIC_VPALiD : InstrItinClass;
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def IIC_VPALiQ : InstrItinClass;
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def IIC_VMULi16D : InstrItinClass;
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def IIC_VMULi32D : InstrItinClass;
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def IIC_VMULi16Q : InstrItinClass;
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def IIC_VMULi32Q : InstrItinClass;
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def IIC_VMACi16D : InstrItinClass;
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def IIC_VMACi32D : InstrItinClass;
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def IIC_VMACi16Q : InstrItinClass;
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def IIC_VMACi32Q : InstrItinClass;
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def IIC_VEXTD : InstrItinClass;
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def IIC_VEXTQ : InstrItinClass;
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def IIC_VTB1 : InstrItinClass;
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def IIC_VTB2 : InstrItinClass;
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def IIC_VTB3 : InstrItinClass;
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def IIC_VTB4 : InstrItinClass;
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def IIC_VTBX1 : InstrItinClass;
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def IIC_VTBX2 : InstrItinClass;
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def IIC_VTBX3 : InstrItinClass;
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def IIC_VTBX4 : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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def GenericItineraries : ProcessorItineraries<[], []>;
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include "ARMScheduleV6.td"
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include "ARMScheduleA8.td"
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include "ARMScheduleA9.td"
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