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https://github.com/c64scene-ar/llvm-6502.git
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d6ac8e9a03
latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.7 KiB
LLVM
52 lines
1.7 KiB
LLVM
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
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; CHECK: addl ([[reg:%[a-z]+]])
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; CHECK-NEXT: addl $4, [[reg]]
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; Test for the FixupLEAs pre-emit pass.
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; An LEA should NOT be substituted for the ADD instruction
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; that increments the array pointer if it is greater than 5 instructions
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; away from the memory reference that uses it.
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; Original C code: clang -m32 -S -O2
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;int test(int n, int * array, int * m, int * array2)
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;{
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; int i, j = 0;
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; int sum = 0;
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; for (i = 0, j = 0; i < n;) {
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; ++i;
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; *m += array2[j++];
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; sum += array[i];
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; }
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; return sum;
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;}
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define i32 @test(i32 %n, i32* nocapture %array, i32* nocapture %m, i32* nocapture %array2) #0 {
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entry:
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%cmp7 = icmp sgt i32 %n, 0
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br i1 %cmp7, label %for.body.lr.ph, label %for.end
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for.body.lr.ph: ; preds = %entry
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%.pre = load i32* %m, align 4
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br label %for.body
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for.body: ; preds = %for.body, %for.body.lr.ph
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%0 = phi i32 [ %.pre, %for.body.lr.ph ], [ %add, %for.body ]
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%sum.010 = phi i32 [ 0, %for.body.lr.ph ], [ %add3, %for.body ]
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%j.09 = phi i32 [ 0, %for.body.lr.ph ], [ %inc1, %for.body ]
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%inc1 = add nsw i32 %j.09, 1
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%arrayidx = getelementptr inbounds i32* %array2, i32 %j.09
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%1 = load i32* %arrayidx, align 4
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%add = add nsw i32 %0, %1
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store i32 %add, i32* %m, align 4
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%arrayidx2 = getelementptr inbounds i32* %array, i32 %inc1
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%2 = load i32* %arrayidx2, align 4
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%add3 = add nsw i32 %2, %sum.010
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%exitcond = icmp eq i32 %inc1, %n
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%sum.0.lcssa = phi i32 [ 0, %entry ], [ %add3, %for.body ]
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ret i32 %sum.0.lcssa
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}
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