mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
087ab613f4
This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
193 lines
4.7 KiB
LLVM
193 lines
4.7 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
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; Splat patterns below
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define <4 x i32> @shl4(<4 x i32> %A) nounwind {
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entry:
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; CHECK: shl4
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; CHECK: pslld
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; CHECK: padd
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; CHECK: ret
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%B = shl <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2>
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%C = shl <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1>
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%K = xor <4 x i32> %B, %C
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ret <4 x i32> %K
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}
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define <4 x i32> @shr4(<4 x i32> %A) nounwind {
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entry:
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; CHECK: shr4
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; CHECK: psrld
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; CHECK-NEXT: psrld
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; CHECK: ret
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%B = lshr <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2>
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%C = lshr <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1>
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%K = xor <4 x i32> %B, %C
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ret <4 x i32> %K
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}
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define <4 x i32> @sra4(<4 x i32> %A) nounwind {
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entry:
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; CHECK: sra4
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; CHECK: psrad
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; CHECK-NEXT: psrad
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; CHECK: ret
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%B = ashr <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2>
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%C = ashr <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1>
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%K = xor <4 x i32> %B, %C
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ret <4 x i32> %K
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}
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define <2 x i64> @shl2(<2 x i64> %A) nounwind {
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entry:
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; CHECK: shl2
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; CHECK: psllq
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; CHECK-NEXT: psllq
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; CHECK: ret
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%B = shl <2 x i64> %A, < i64 2, i64 2>
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%C = shl <2 x i64> %A, < i64 9, i64 9>
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%K = xor <2 x i64> %B, %C
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ret <2 x i64> %K
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}
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define <2 x i64> @shr2(<2 x i64> %A) nounwind {
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entry:
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; CHECK: shr2
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; CHECK: psrlq
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; CHECK-NEXT: psrlq
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; CHECK: ret
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%B = lshr <2 x i64> %A, < i64 8, i64 8>
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%C = lshr <2 x i64> %A, < i64 1, i64 1>
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%K = xor <2 x i64> %B, %C
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ret <2 x i64> %K
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}
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define <8 x i16> @shl8(<8 x i16> %A) nounwind {
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entry:
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; CHECK: shl8
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; CHECK: psllw
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; CHECK: padd
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; CHECK: ret
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%B = shl <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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%C = shl <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%K = xor <8 x i16> %B, %C
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ret <8 x i16> %K
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}
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define <8 x i16> @shr8(<8 x i16> %A) nounwind {
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entry:
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; CHECK: shr8
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; CHECK: psrlw
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; CHECK-NEXT: psrlw
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; CHECK: ret
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%B = lshr <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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%C = lshr <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%K = xor <8 x i16> %B, %C
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ret <8 x i16> %K
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}
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define <8 x i16> @sra8(<8 x i16> %A) nounwind {
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entry:
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; CHECK: sra8
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; CHECK: psraw
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; CHECK-NEXT: psraw
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; CHECK: ret
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%B = ashr <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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%C = ashr <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%K = xor <8 x i16> %B, %C
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ret <8 x i16> %K
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}
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; non-splat test
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define <8 x i16> @sll8_nosplat(<8 x i16> %A) nounwind {
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entry:
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; CHECK: sll8_nosplat
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; CHECK-NOT: psll
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; CHECK-NOT: psll
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; CHECK: ret
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%B = shl <8 x i16> %A, < i16 1, i16 2, i16 3, i16 6, i16 2, i16 2, i16 2, i16 2>
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%C = shl <8 x i16> %A, < i16 9, i16 7, i16 5, i16 1, i16 4, i16 1, i16 1, i16 1>
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%K = xor <8 x i16> %B, %C
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ret <8 x i16> %K
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}
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define <2 x i64> @shr2_nosplat(<2 x i64> %A) nounwind {
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entry:
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; CHECK: shr2_nosplat
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; CHECK-NOT: psrlq
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; CHECK-NOT: psrlq
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; CHECK: ret
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%B = lshr <2 x i64> %A, < i64 8, i64 1>
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%C = lshr <2 x i64> %A, < i64 1, i64 0>
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%K = xor <2 x i64> %B, %C
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ret <2 x i64> %K
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}
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; Other shifts
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define <2 x i32> @shl2_other(<2 x i32> %A) nounwind {
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entry:
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; CHECK: shl2_other
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; CHECK: psllq
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; CHECK: ret
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%B = shl <2 x i32> %A, < i32 2, i32 2>
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%C = shl <2 x i32> %A, < i32 9, i32 9>
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%K = xor <2 x i32> %B, %C
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ret <2 x i32> %K
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}
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define <2 x i32> @shr2_other(<2 x i32> %A) nounwind {
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entry:
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; CHECK: shr2_other
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; CHECK: psrlq
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; CHECK: ret
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%B = lshr <2 x i32> %A, < i32 8, i32 8>
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%C = lshr <2 x i32> %A, < i32 1, i32 1>
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%K = xor <2 x i32> %B, %C
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ret <2 x i32> %K
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}
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define <16 x i8> @shl9(<16 x i8> %A) nounwind {
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%B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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ret <16 x i8> %B
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; CHECK-LABEL: shl9:
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; CHECK: psllw $3
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; CHECK: pand
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; CHECK: ret
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}
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define <16 x i8> @shr9(<16 x i8> %A) nounwind {
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%B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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ret <16 x i8> %B
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; CHECK-LABEL: shr9:
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; CHECK: psrlw $3
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; CHECK: pand
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; CHECK: ret
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}
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define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
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%B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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ret <16 x i8> %B
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; CHECK-LABEL: sra_v16i8_7:
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; CHECK: pxor
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; CHECK: pcmpgtb
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; CHECK: ret
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}
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define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind {
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%B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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ret <16 x i8> %B
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; CHECK-LABEL: sra_v16i8:
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; CHECK: psrlw $3
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; CHECK: pand
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; CHECK: pxor
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; CHECK: psubb
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; CHECK: ret
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}
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