mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 19:29:22 +00:00
922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
1.7 KiB
LLVM
74 lines
1.7 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -asm-verbose=0 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
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target triple = "i686-pc-linux-gnu"
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define zeroext i16 @test1(i16 zeroext %x) nounwind {
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entry:
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%div = udiv i16 %x, 33
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ret i16 %div
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; CHECK: test1:
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; CHECK: imull $63551, %eax, %eax
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; CHECK-NEXT: shrl $21, %eax
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; CHECK-NEXT: ret
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}
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define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) nounwind readnone ssp noredzone {
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entry:
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%div = udiv i16 %c, 3
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ret i16 %div
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; CHECK: test2:
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; CHECK: imull $43691, %eax, %eax
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; CHECK-NEXT: shrl $17, %eax
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; CHECK-NEXT: ret
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}
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define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp noredzone {
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entry:
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%div = udiv i8 %c, 3
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ret i8 %div
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; CHECK: test3:
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; CHECK: movzbl 8(%esp), %eax
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; CHECK-NEXT: imull $171, %eax, %eax
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; CHECK-NEXT: shrl $9, %eax
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; CHECK-NEXT: ret
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}
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define signext i16 @test4(i16 signext %x) nounwind {
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entry:
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%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
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ret i16 %div
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; CHECK: test4:
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; CHECK: imull $1986, %eax, %
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}
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define i32 @test5(i32 %A) nounwind {
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%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
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ret i32 %tmp1
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; CHECK: test5:
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; CHECK: movl $365384439, %eax
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; CHECK: mull 4(%esp)
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}
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define signext i16 @test6(i16 signext %x) nounwind {
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entry:
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%div = sdiv i16 %x, 10
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ret i16 %div
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; CHECK: test6:
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; CHECK: imull $26215, %eax, %eax
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; CHECK: shrl $31, %ecx
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; CHECK: sarl $18, %eax
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}
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define i32 @test7(i32 %x) nounwind {
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%div = udiv i32 %x, 28
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ret i32 %div
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; CHECK: test7:
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; CHECK: shrl $2
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; CHECK: movl $613566757
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; CHECK: mull
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; CHECK-NOT: shrl
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; CHECK: ret
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}
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