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https://github.com/c64scene-ar/llvm-6502.git
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Previously we were abandonning the attempt, leading to some combination of extra work (when selection of a load/store fails completely) and inferior code (when this leads to a real memcpy call instead of inlining). rdar://problem/17187463 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210520 91177308-0d34-0410-b5e6-96231b3b80d8
1983 lines
61 KiB
C++
1983 lines
61 KiB
C++
//===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AArch64-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// AArch64GenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64TargetMachine.h"
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#include "AArch64Subtarget.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GetElementPtrTypeIterator.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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namespace {
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class AArch64FastISel : public FastISel {
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class Address {
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public:
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typedef enum {
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RegBase,
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FrameIndexBase
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} BaseKind;
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private:
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BaseKind Kind;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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public:
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Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
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void setKind(BaseKind K) { Kind = K; }
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BaseKind getKind() const { return Kind; }
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bool isRegBase() const { return Kind == RegBase; }
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bool isFIBase() const { return Kind == FrameIndexBase; }
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void setReg(unsigned Reg) {
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assert(isRegBase() && "Invalid base register access!");
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Base.Reg = Reg;
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}
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unsigned getReg() const {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setFI(unsigned FI) {
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assert(isFIBase() && "Invalid base frame index access!");
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Base.FI = FI;
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}
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unsigned getFI() const {
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assert(isFIBase() && "Invalid base frame index access!");
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return Base.FI;
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}
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void setOffset(int64_t O) { Offset = O; }
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int64_t getOffset() { return Offset; }
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bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
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};
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/// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const AArch64Subtarget *Subtarget;
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LLVMContext *Context;
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private:
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// Selection routines.
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bool SelectLoad(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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bool SelectIndirectBr(const Instruction *I);
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bool SelectCmp(const Instruction *I);
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bool SelectSelect(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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bool SelectFPToInt(const Instruction *I, bool Signed);
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bool SelectIntToFP(const Instruction *I, bool Signed);
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bool SelectRem(const Instruction *I, unsigned ISDOpcode);
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bool SelectCall(const Instruction *I, const char *IntrMemName);
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bool SelectIntrinsicCall(const IntrinsicInst &I);
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bool SelectRet(const Instruction *I);
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bool SelectTrunc(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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bool SelectMul(const Instruction *I);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
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bool ComputeAddress(const Value *Obj, Address &Addr);
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bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
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bool UseUnscaled);
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void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
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unsigned Flags, bool UseUnscaled);
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bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
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bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
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unsigned Alignment);
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// Emit functions.
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bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
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bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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bool UseUnscaled = false);
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bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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bool UseUnscaled = false);
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unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned AArch64MaterializeGV(const GlobalValue *GV);
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// Call handling routines.
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private:
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
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bool ProcessCallArgs(SmallVectorImpl<Value *> &Args,
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SmallVectorImpl<unsigned> &ArgRegs,
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SmallVectorImpl<MVT> &ArgVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
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SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC,
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unsigned &NumBytes);
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bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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const Instruction *I, CallingConv::ID CC, unsigned &NumBytes);
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public:
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// Backend specific FastISel code.
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unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
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unsigned TargetMaterializeConstant(const Constant *C) override;
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explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo) {
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Subtarget = &TM.getSubtarget<AArch64Subtarget>();
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Context = &funcInfo.Fn->getContext();
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}
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bool TargetSelectInstruction(const Instruction *I) override;
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#include "AArch64GenFastISel.inc"
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};
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} // end anonymous namespace
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#include "AArch64GenCallingConv.inc"
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CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
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if (CC == CallingConv::WebKit_JS)
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return CC_AArch64_WebKit_JS;
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return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
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}
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unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
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"Alloca should always return a pointer.");
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// Don't handle dynamic allocas.
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if (!FuncInfo.StaticAllocaMap.count(AI))
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return 0;
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DenseMap<const AllocaInst *, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addFrameIndex(SI->second)
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.addImm(0)
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.addImm(0);
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return ResultReg;
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}
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return 0;
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}
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unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
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if (VT != MVT::f32 && VT != MVT::f64)
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return 0;
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const APFloat Val = CFP->getValueAPF();
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bool is64bit = (VT == MVT::f64);
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// This checks to see if we can use FMOV instructions to materialize
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// a constant, otherwise we have to materialize via the constant pool.
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if (TLI.isFPImmLegal(Val, VT)) {
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int Imm;
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unsigned Opc;
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if (is64bit) {
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Imm = AArch64_AM::getFP64Imm(Val);
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Opc = AArch64::FMOVDi;
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} else {
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Imm = AArch64_AM::getFP32Imm(Val);
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Opc = AArch64::FMOVSi;
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}
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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.addImm(Imm);
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return ResultReg;
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}
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// Materialize via constant pool. MachineConstantPool wants an explicit
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// alignment.
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unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
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if (Align == 0)
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Align = DL.getTypeAllocSize(CFP->getType());
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unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
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unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg).addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGE);
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unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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.addReg(ADRPReg)
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.addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
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return ResultReg;
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}
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unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
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// We can't handle thread-local variables quickly yet.
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if (GV->isThreadLocal())
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return 0;
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// MachO still uses GOT for large code-model accesses, but ELF requires
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// movz/movk sequences, which FastISel doesn't handle yet.
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if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
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return 0;
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unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
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EVT DestEVT = TLI.getValueType(GV->getType(), true);
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if (!DestEVT.isSimple())
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return 0;
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unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
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unsigned ResultReg;
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if (OpFlags & AArch64II::MO_GOT) {
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// ADRP + LDRX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
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ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
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AArch64II::MO_NC);
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} else {
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// ADRP + ADDX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg).addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
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ResultReg = createResultReg(&AArch64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
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.addImm(0);
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}
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return ResultReg;
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}
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unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
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EVT CEVT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!CEVT.isSimple())
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return 0;
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MVT VT = CEVT.getSimpleVT();
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// FIXME: Handle ConstantInt.
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return AArch64MaterializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return AArch64MaterializeGV(GV);
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return 0;
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}
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// Computes the address to get to an object.
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bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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// Don't walk into other basic blocks unless the object is an alloca from
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// another block, otherwise it may not have a virtual register assigned.
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if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
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FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
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Opcode = I->getOpcode();
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U = I;
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}
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} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
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Opcode = C->getOpcode();
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U = C;
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}
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if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
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if (Ty->getAddressSpace() > 255)
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// Fast instruction selection doesn't support the special
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// address spaces.
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return false;
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switch (Opcode) {
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default:
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break;
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case Instruction::BitCast: {
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// Look through bitcasts.
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return ComputeAddress(U->getOperand(0), Addr);
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}
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case Instruction::IntToPtr: {
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return ComputeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::PtrToInt: {
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return ComputeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::GetElementPtr: {
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Address SavedAddr = Addr;
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uint64_t TmpOffset = Addr.getOffset();
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// Iterate through the GEP folding the constants into offsets where
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// we can.
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gep_type_iterator GTI = gep_type_begin(U);
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for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
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++i, ++GTI) {
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const Value *Op = *i;
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if (StructType *STy = dyn_cast<StructType>(*GTI)) {
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const StructLayout *SL = DL.getStructLayout(STy);
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unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
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TmpOffset += SL->getElementOffset(Idx);
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} else {
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uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
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for (;;) {
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
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// Constant-offset addressing.
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TmpOffset += CI->getSExtValue() * S;
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break;
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}
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if (canFoldAddIntoGEP(U, Op)) {
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// A compatible add with a constant operand. Fold the constant.
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ConstantInt *CI =
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cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
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TmpOffset += CI->getSExtValue() * S;
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// Iterate on the other operand.
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Op = cast<AddOperator>(Op)->getOperand(0);
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continue;
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}
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// Unsupported
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goto unsupported_gep;
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}
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}
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}
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// Try to grab the base operand now.
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Addr.setOffset(TmpOffset);
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if (ComputeAddress(U->getOperand(0), Addr))
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return true;
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// We failed, restore everything and try the other options.
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Addr = SavedAddr;
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unsupported_gep:
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break;
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}
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case Instruction::Alloca: {
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const AllocaInst *AI = cast<AllocaInst>(Obj);
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DenseMap<const AllocaInst *, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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Addr.setKind(Address::FrameIndexBase);
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Addr.setFI(SI->second);
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return true;
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}
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break;
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}
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}
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// Try to get this in a register if nothing else has worked.
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if (!Addr.isValid())
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Addr.setReg(getRegForValue(Obj));
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return Addr.isValid();
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}
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bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
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EVT evt = TLI.getValueType(Ty, true);
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// Only handle simple types.
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if (evt == MVT::Other || !evt.isSimple())
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return false;
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VT = evt.getSimpleVT();
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// This is a legal type, but it's not something we handle in fast-isel.
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if (VT == MVT::f128)
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return false;
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// Handle all other legal types, i.e. a register that will directly hold this
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// value.
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return TLI.isTypeLegal(VT);
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}
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bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
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if (isTypeLegal(Ty, VT))
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return true;
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now. For stores, this reflects truncation.
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if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
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return true;
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return false;
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}
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bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
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int64_t ScaleFactor, bool UseUnscaled) {
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bool needsLowering = false;
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int64_t Offset = Addr.getOffset();
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switch (VT.SimpleTy) {
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default:
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return false;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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case MVT::f32:
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case MVT::f64:
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if (!UseUnscaled)
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// Using scaled, 12-bit, unsigned immediate offsets.
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needsLowering = ((Offset & 0xfff) != Offset);
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else
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// Using unscaled, 9-bit, signed immediate offsets.
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needsLowering = (Offset > 256 || Offset < -256);
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break;
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}
|
|
|
|
//If this is a stack pointer and the offset needs to be simplified then put
|
|
// the alloca address into a register, set the base type back to register and
|
|
// continue. This should almost never happen.
|
|
if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
|
|
unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
|
|
ResultReg)
|
|
.addFrameIndex(Addr.getFI())
|
|
.addImm(0)
|
|
.addImm(0);
|
|
Addr.setKind(Address::RegBase);
|
|
Addr.setReg(ResultReg);
|
|
}
|
|
|
|
// Since the offset is too large for the load/store instruction get the
|
|
// reg+offset into a register.
|
|
if (needsLowering) {
|
|
uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
|
|
unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
|
|
UnscaledOffset, MVT::i64);
|
|
if (ResultReg == 0)
|
|
return false;
|
|
Addr.setReg(ResultReg);
|
|
Addr.setOffset(0);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
|
|
const MachineInstrBuilder &MIB,
|
|
unsigned Flags, bool UseUnscaled) {
|
|
int64_t Offset = Addr.getOffset();
|
|
// Frame base works a bit differently. Handle it separately.
|
|
if (Addr.getKind() == Address::FrameIndexBase) {
|
|
int FI = Addr.getFI();
|
|
// FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
|
|
// and alignment should be based on the VT.
|
|
MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(FI, Offset), Flags,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
|
|
// Now add the rest of the operands.
|
|
MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
|
|
} else {
|
|
// Now add the rest of the operands.
|
|
MIB.addReg(Addr.getReg());
|
|
MIB.addImm(Offset);
|
|
}
|
|
}
|
|
|
|
bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
|
|
bool UseUnscaled) {
|
|
// Negative offsets require unscaled, 9-bit, signed immediate offsets.
|
|
// Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
|
|
if (!UseUnscaled && Addr.getOffset() < 0)
|
|
UseUnscaled = true;
|
|
|
|
unsigned Opc;
|
|
const TargetRegisterClass *RC;
|
|
bool VTIsi1 = false;
|
|
int64_t ScaleFactor = 0;
|
|
switch (VT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i1:
|
|
VTIsi1 = true;
|
|
// Intentional fall-through.
|
|
case MVT::i8:
|
|
Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
|
|
RC = &AArch64::GPR32RegClass;
|
|
ScaleFactor = 1;
|
|
break;
|
|
case MVT::i16:
|
|
Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
|
|
RC = &AArch64::GPR32RegClass;
|
|
ScaleFactor = 2;
|
|
break;
|
|
case MVT::i32:
|
|
Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
|
|
RC = &AArch64::GPR32RegClass;
|
|
ScaleFactor = 4;
|
|
break;
|
|
case MVT::i64:
|
|
Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
|
|
RC = &AArch64::GPR64RegClass;
|
|
ScaleFactor = 8;
|
|
break;
|
|
case MVT::f32:
|
|
Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
|
|
RC = TLI.getRegClassFor(VT);
|
|
ScaleFactor = 4;
|
|
break;
|
|
case MVT::f64:
|
|
Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
|
|
RC = TLI.getRegClassFor(VT);
|
|
ScaleFactor = 8;
|
|
break;
|
|
}
|
|
// Scale the offset.
|
|
if (!UseUnscaled) {
|
|
int64_t Offset = Addr.getOffset();
|
|
if (Offset & (ScaleFactor - 1))
|
|
// Retry using an unscaled, 9-bit, signed immediate offset.
|
|
return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
|
|
|
|
Addr.setOffset(Offset / ScaleFactor);
|
|
}
|
|
|
|
// Simplify this down to something we can handle.
|
|
if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
|
|
return false;
|
|
|
|
// Create the base instruction, then add the operands.
|
|
ResultReg = createResultReg(RC);
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(Opc), ResultReg);
|
|
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
|
|
|
|
// Loading an i1 requires special handling.
|
|
if (VTIsi1) {
|
|
MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
|
|
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
|
ANDReg)
|
|
.addReg(ResultReg)
|
|
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
|
ResultReg = ANDReg;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectLoad(const Instruction *I) {
|
|
MVT VT;
|
|
// Verify we have a legal type before going any further. Currently, we handle
|
|
// simple types that will directly fit in a register (i32/f32/i64/f64) or
|
|
// those that can be sign or zero-extended to a basic operation (i1/i8/i16).
|
|
if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
|
|
return false;
|
|
|
|
// See if we can handle this address.
|
|
Address Addr;
|
|
if (!ComputeAddress(I->getOperand(0), Addr))
|
|
return false;
|
|
|
|
unsigned ResultReg;
|
|
if (!EmitLoad(VT, ResultReg, Addr))
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
|
|
bool UseUnscaled) {
|
|
// Negative offsets require unscaled, 9-bit, signed immediate offsets.
|
|
// Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
|
|
if (!UseUnscaled && Addr.getOffset() < 0)
|
|
UseUnscaled = true;
|
|
|
|
unsigned StrOpc;
|
|
bool VTIsi1 = false;
|
|
int64_t ScaleFactor = 0;
|
|
// Using scaled, 12-bit, unsigned immediate offsets.
|
|
switch (VT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i1:
|
|
VTIsi1 = true;
|
|
case MVT::i8:
|
|
StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
|
|
ScaleFactor = 1;
|
|
break;
|
|
case MVT::i16:
|
|
StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
|
|
ScaleFactor = 2;
|
|
break;
|
|
case MVT::i32:
|
|
StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
|
|
ScaleFactor = 4;
|
|
break;
|
|
case MVT::i64:
|
|
StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
|
|
ScaleFactor = 8;
|
|
break;
|
|
case MVT::f32:
|
|
StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
|
|
ScaleFactor = 4;
|
|
break;
|
|
case MVT::f64:
|
|
StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
|
|
ScaleFactor = 8;
|
|
break;
|
|
}
|
|
// Scale the offset.
|
|
if (!UseUnscaled) {
|
|
int64_t Offset = Addr.getOffset();
|
|
if (Offset & (ScaleFactor - 1))
|
|
// Retry using an unscaled, 9-bit, signed immediate offset.
|
|
return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
|
|
|
|
Addr.setOffset(Offset / ScaleFactor);
|
|
}
|
|
|
|
// Simplify this down to something we can handle.
|
|
if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
|
|
return false;
|
|
|
|
// Storing an i1 requires special handling.
|
|
if (VTIsi1) {
|
|
MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
|
|
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
|
ANDReg)
|
|
.addReg(SrcReg)
|
|
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
|
SrcReg = ANDReg;
|
|
}
|
|
// Create the base instruction, then add the operands.
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(StrOpc)).addReg(SrcReg);
|
|
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectStore(const Instruction *I) {
|
|
MVT VT;
|
|
Value *Op0 = I->getOperand(0);
|
|
// Verify we have a legal type before going any further. Currently, we handle
|
|
// simple types that will directly fit in a register (i32/f32/i64/f64) or
|
|
// those that can be sign or zero-extended to a basic operation (i1/i8/i16).
|
|
if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
|
|
cast<StoreInst>(I)->isAtomic())
|
|
return false;
|
|
|
|
// Get the value to be stored into a register.
|
|
unsigned SrcReg = getRegForValue(Op0);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
// See if we can handle this address.
|
|
Address Addr;
|
|
if (!ComputeAddress(I->getOperand(1), Addr))
|
|
return false;
|
|
|
|
if (!EmitStore(VT, SrcReg, Addr))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
|
|
switch (Pred) {
|
|
case CmpInst::FCMP_ONE:
|
|
case CmpInst::FCMP_UEQ:
|
|
default:
|
|
// AL is our "false" for now. The other two need more compares.
|
|
return AArch64CC::AL;
|
|
case CmpInst::ICMP_EQ:
|
|
case CmpInst::FCMP_OEQ:
|
|
return AArch64CC::EQ;
|
|
case CmpInst::ICMP_SGT:
|
|
case CmpInst::FCMP_OGT:
|
|
return AArch64CC::GT;
|
|
case CmpInst::ICMP_SGE:
|
|
case CmpInst::FCMP_OGE:
|
|
return AArch64CC::GE;
|
|
case CmpInst::ICMP_UGT:
|
|
case CmpInst::FCMP_UGT:
|
|
return AArch64CC::HI;
|
|
case CmpInst::FCMP_OLT:
|
|
return AArch64CC::MI;
|
|
case CmpInst::ICMP_ULE:
|
|
case CmpInst::FCMP_OLE:
|
|
return AArch64CC::LS;
|
|
case CmpInst::FCMP_ORD:
|
|
return AArch64CC::VC;
|
|
case CmpInst::FCMP_UNO:
|
|
return AArch64CC::VS;
|
|
case CmpInst::FCMP_UGE:
|
|
return AArch64CC::PL;
|
|
case CmpInst::ICMP_SLT:
|
|
case CmpInst::FCMP_ULT:
|
|
return AArch64CC::LT;
|
|
case CmpInst::ICMP_SLE:
|
|
case CmpInst::FCMP_ULE:
|
|
return AArch64CC::LE;
|
|
case CmpInst::FCMP_UNE:
|
|
case CmpInst::ICMP_NE:
|
|
return AArch64CC::NE;
|
|
case CmpInst::ICMP_UGE:
|
|
return AArch64CC::HS;
|
|
case CmpInst::ICMP_ULT:
|
|
return AArch64CC::LO;
|
|
}
|
|
}
|
|
|
|
bool AArch64FastISel::SelectBranch(const Instruction *I) {
|
|
const BranchInst *BI = cast<BranchInst>(I);
|
|
MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
|
|
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
|
|
|
|
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
|
|
if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
|
|
// We may not handle every CC for now.
|
|
AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
|
|
if (CC == AArch64CC::AL)
|
|
return false;
|
|
|
|
// Emit the cmp.
|
|
if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
|
|
return false;
|
|
|
|
// Emit the branch.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
} else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
|
|
MVT SrcVT;
|
|
if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
|
|
(isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
|
|
unsigned CondReg = getRegForValue(TI->getOperand(0));
|
|
if (CondReg == 0)
|
|
return false;
|
|
|
|
// Issue an extract_subreg to get the lower 32-bits.
|
|
if (SrcVT == MVT::i64)
|
|
CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
|
|
AArch64::sub_32);
|
|
|
|
MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
|
|
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::ANDWri), ANDReg)
|
|
.addReg(CondReg)
|
|
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBSWri))
|
|
.addReg(ANDReg)
|
|
.addReg(ANDReg)
|
|
.addImm(0)
|
|
.addImm(0);
|
|
|
|
unsigned CC = AArch64CC::NE;
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
std::swap(TBB, FBB);
|
|
CC = AArch64CC::EQ;
|
|
}
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
} else if (const ConstantInt *CI =
|
|
dyn_cast<ConstantInt>(BI->getCondition())) {
|
|
uint64_t Imm = CI->getZExtValue();
|
|
MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
|
|
.addMBB(Target);
|
|
FuncInfo.MBB->addSuccessor(Target);
|
|
return true;
|
|
}
|
|
|
|
unsigned CondReg = getRegForValue(BI->getCondition());
|
|
if (CondReg == 0)
|
|
return false;
|
|
|
|
// We've been divorced from our compare! Our block was split, and
|
|
// now our compare lives in a predecessor block. We musn't
|
|
// re-compare here, as the children of the compare aren't guaranteed
|
|
// live across the block boundary (we *could* check for this).
|
|
// Regardless, the compare has been done in the predecessor block,
|
|
// and it left a value for us in a virtual register. Ergo, we test
|
|
// the one-bit value left in the virtual register.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
|
|
AArch64::WZR)
|
|
.addReg(CondReg)
|
|
.addImm(0)
|
|
.addImm(0);
|
|
|
|
unsigned CC = AArch64CC::NE;
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
std::swap(TBB, FBB);
|
|
CC = AArch64CC::EQ;
|
|
}
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
FuncInfo.MBB->addSuccessor(TBB);
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
|
|
const IndirectBrInst *BI = cast<IndirectBrInst>(I);
|
|
unsigned AddrReg = getRegForValue(BI->getOperand(0));
|
|
if (AddrReg == 0)
|
|
return false;
|
|
|
|
// Emit the indirect branch.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
|
|
.addReg(AddrReg);
|
|
|
|
// Make sure the CFG is up-to-date.
|
|
for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
|
|
FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
|
|
Type *Ty = Src1Value->getType();
|
|
EVT SrcEVT = TLI.getValueType(Ty, true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
|
|
// Check to see if the 2nd operand is a constant that we can encode directly
|
|
// in the compare.
|
|
uint64_t Imm;
|
|
bool UseImm = false;
|
|
bool isNegativeImm = false;
|
|
if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
|
|
if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
|
|
SrcVT == MVT::i8 || SrcVT == MVT::i1) {
|
|
const APInt &CIVal = ConstInt->getValue();
|
|
|
|
Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
|
|
if (CIVal.isNegative()) {
|
|
isNegativeImm = true;
|
|
Imm = -Imm;
|
|
}
|
|
// FIXME: We can handle more immediates using shifts.
|
|
UseImm = ((Imm & 0xfff) == Imm);
|
|
}
|
|
} else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
|
|
if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
|
|
if (ConstFP->isZero() && !ConstFP->isNegative())
|
|
UseImm = true;
|
|
}
|
|
|
|
unsigned ZReg;
|
|
unsigned CmpOpc;
|
|
bool isICmp = true;
|
|
bool needsExt = false;
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
needsExt = true;
|
|
// Intentional fall-through.
|
|
case MVT::i32:
|
|
ZReg = AArch64::WZR;
|
|
if (UseImm)
|
|
CmpOpc = isNegativeImm ? AArch64::ADDSWri : AArch64::SUBSWri;
|
|
else
|
|
CmpOpc = AArch64::SUBSWrr;
|
|
break;
|
|
case MVT::i64:
|
|
ZReg = AArch64::XZR;
|
|
if (UseImm)
|
|
CmpOpc = isNegativeImm ? AArch64::ADDSXri : AArch64::SUBSXri;
|
|
else
|
|
CmpOpc = AArch64::SUBSXrr;
|
|
break;
|
|
case MVT::f32:
|
|
isICmp = false;
|
|
CmpOpc = UseImm ? AArch64::FCMPSri : AArch64::FCMPSrr;
|
|
break;
|
|
case MVT::f64:
|
|
isICmp = false;
|
|
CmpOpc = UseImm ? AArch64::FCMPDri : AArch64::FCMPDrr;
|
|
break;
|
|
}
|
|
|
|
unsigned SrcReg1 = getRegForValue(Src1Value);
|
|
if (SrcReg1 == 0)
|
|
return false;
|
|
|
|
unsigned SrcReg2;
|
|
if (!UseImm) {
|
|
SrcReg2 = getRegForValue(Src2Value);
|
|
if (SrcReg2 == 0)
|
|
return false;
|
|
}
|
|
|
|
// We have i1, i8, or i16, we need to either zero extend or sign extend.
|
|
if (needsExt) {
|
|
SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
|
|
if (SrcReg1 == 0)
|
|
return false;
|
|
if (!UseImm) {
|
|
SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
|
|
if (SrcReg2 == 0)
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (isICmp) {
|
|
if (UseImm)
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
|
|
.addReg(ZReg)
|
|
.addReg(SrcReg1)
|
|
.addImm(Imm)
|
|
.addImm(0);
|
|
else
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
|
|
.addReg(ZReg)
|
|
.addReg(SrcReg1)
|
|
.addReg(SrcReg2);
|
|
} else {
|
|
if (UseImm)
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
|
|
.addReg(SrcReg1);
|
|
else
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
|
|
.addReg(SrcReg1)
|
|
.addReg(SrcReg2);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectCmp(const Instruction *I) {
|
|
const CmpInst *CI = cast<CmpInst>(I);
|
|
|
|
// We may not handle every CC for now.
|
|
AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
|
|
if (CC == AArch64CC::AL)
|
|
return false;
|
|
|
|
// Emit the cmp.
|
|
if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
|
|
return false;
|
|
|
|
// Now set a register based on the comparison.
|
|
AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
|
|
unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
|
|
ResultReg)
|
|
.addReg(AArch64::WZR)
|
|
.addReg(AArch64::WZR)
|
|
.addImm(invertedCC);
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectSelect(const Instruction *I) {
|
|
const SelectInst *SI = cast<SelectInst>(I);
|
|
|
|
EVT DestEVT = TLI.getValueType(SI->getType(), true);
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
|
|
DestVT != MVT::f64)
|
|
return false;
|
|
|
|
unsigned CondReg = getRegForValue(SI->getCondition());
|
|
if (CondReg == 0)
|
|
return false;
|
|
unsigned TrueReg = getRegForValue(SI->getTrueValue());
|
|
if (TrueReg == 0)
|
|
return false;
|
|
unsigned FalseReg = getRegForValue(SI->getFalseValue());
|
|
if (FalseReg == 0)
|
|
return false;
|
|
|
|
|
|
MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
|
|
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
|
ANDReg)
|
|
.addReg(CondReg)
|
|
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
|
|
.addReg(ANDReg)
|
|
.addReg(ANDReg)
|
|
.addImm(0)
|
|
.addImm(0);
|
|
|
|
unsigned SelectOpc;
|
|
switch (DestVT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i32:
|
|
SelectOpc = AArch64::CSELWr;
|
|
break;
|
|
case MVT::i64:
|
|
SelectOpc = AArch64::CSELXr;
|
|
break;
|
|
case MVT::f32:
|
|
SelectOpc = AArch64::FCSELSrrr;
|
|
break;
|
|
case MVT::f64:
|
|
SelectOpc = AArch64::FCSELDrrr;
|
|
break;
|
|
}
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
|
|
ResultReg)
|
|
.addReg(TrueReg)
|
|
.addReg(FalseReg)
|
|
.addImm(AArch64CC::NE);
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectFPExt(const Instruction *I) {
|
|
Value *V = I->getOperand(0);
|
|
if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
|
|
return false;
|
|
|
|
unsigned Op = getRegForValue(V);
|
|
if (Op == 0)
|
|
return false;
|
|
|
|
unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
|
|
ResultReg).addReg(Op);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
|
|
Value *V = I->getOperand(0);
|
|
if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
|
|
return false;
|
|
|
|
unsigned Op = getRegForValue(V);
|
|
if (Op == 0)
|
|
return false;
|
|
|
|
unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
|
|
ResultReg).addReg(Op);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
// FPToUI and FPToSI
|
|
bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
|
|
MVT DestVT;
|
|
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(I->getOperand(0));
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
|
if (SrcVT == MVT::f128)
|
|
return false;
|
|
|
|
unsigned Opc;
|
|
if (SrcVT == MVT::f64) {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
|
|
else
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
|
|
} else {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
|
|
else
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
|
|
}
|
|
unsigned ResultReg = createResultReg(
|
|
DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
.addReg(SrcReg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
|
|
MVT DestVT;
|
|
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
|
|
return false;
|
|
assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
|
|
"Unexpected value type.");
|
|
|
|
unsigned SrcReg = getRegForValue(I->getOperand(0));
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
|
|
|
// Handle sign-extension.
|
|
if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
|
|
SrcReg =
|
|
EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
}
|
|
|
|
MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
|
|
: &AArch64::GPR32RegClass);
|
|
|
|
unsigned Opc;
|
|
if (SrcVT == MVT::i64) {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
|
|
else
|
|
Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
|
|
} else {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
|
|
else
|
|
Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
|
|
}
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
.addReg(SrcReg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::ProcessCallArgs(
|
|
SmallVectorImpl<Value *> &Args, SmallVectorImpl<unsigned> &ArgRegs,
|
|
SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
|
|
SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC,
|
|
unsigned &NumBytes) {
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
|
|
CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
NumBytes = CCInfo.getNextStackOffset();
|
|
|
|
// Issue CALLSEQ_START
|
|
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
|
|
.addImm(NumBytes);
|
|
|
|
// Process the args.
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
unsigned Arg = ArgRegs[VA.getValNo()];
|
|
MVT ArgVT = ArgVTs[VA.getValNo()];
|
|
|
|
// Handle arg promotion: SExt, ZExt, AExt.
|
|
switch (VA.getLocInfo()) {
|
|
case CCValAssign::Full:
|
|
break;
|
|
case CCValAssign::SExt: {
|
|
MVT DestVT = VA.getLocVT();
|
|
MVT SrcVT = ArgVT;
|
|
Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ false);
|
|
if (Arg == 0)
|
|
return false;
|
|
break;
|
|
}
|
|
case CCValAssign::AExt:
|
|
// Intentional fall-through.
|
|
case CCValAssign::ZExt: {
|
|
MVT DestVT = VA.getLocVT();
|
|
MVT SrcVT = ArgVT;
|
|
Arg = EmitIntExt(SrcVT, Arg, DestVT, /*isZExt*/ true);
|
|
if (Arg == 0)
|
|
return false;
|
|
break;
|
|
}
|
|
default:
|
|
llvm_unreachable("Unknown arg promotion!");
|
|
}
|
|
|
|
// Now copy/store arg to correct locations.
|
|
if (VA.isRegLoc() && !VA.needsCustom()) {
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
|
|
RegArgs.push_back(VA.getLocReg());
|
|
} else if (VA.needsCustom()) {
|
|
// FIXME: Handle custom args.
|
|
return false;
|
|
} else {
|
|
assert(VA.isMemLoc() && "Assuming store on stack.");
|
|
|
|
// Need to store on the stack.
|
|
unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
|
|
|
|
unsigned BEAlign = 0;
|
|
if (ArgSize < 8 && !Subtarget->isLittleEndian())
|
|
BEAlign = 8 - ArgSize;
|
|
|
|
Address Addr;
|
|
Addr.setKind(Address::RegBase);
|
|
Addr.setReg(AArch64::SP);
|
|
Addr.setOffset(VA.getLocMemOffset() + BEAlign);
|
|
|
|
if (!EmitStore(ArgVT, Arg, Addr))
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
|
|
const Instruction *I, CallingConv::ID CC,
|
|
unsigned &NumBytes) {
|
|
// Issue CALLSEQ_END
|
|
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
|
|
.addImm(NumBytes)
|
|
.addImm(0);
|
|
|
|
// Now the return value.
|
|
if (RetVT != MVT::isVoid) {
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
|
|
CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
|
|
|
|
// Only handle a single return value.
|
|
if (RVLocs.size() != 1)
|
|
return false;
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
MVT CopyVT = RVLocs[0].getValVT();
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY),
|
|
ResultReg).addReg(RVLocs[0].getLocReg());
|
|
UsedRegs.push_back(RVLocs[0].getLocReg());
|
|
|
|
// Finally update the result.
|
|
UpdateValueMap(I, ResultReg);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectCall(const Instruction *I,
|
|
const char *IntrMemName = nullptr) {
|
|
const CallInst *CI = cast<CallInst>(I);
|
|
const Value *Callee = CI->getCalledValue();
|
|
|
|
// Don't handle inline asm or intrinsics.
|
|
if (isa<InlineAsm>(Callee))
|
|
return false;
|
|
|
|
// Only handle global variable Callees.
|
|
const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
|
|
if (!GV)
|
|
return false;
|
|
|
|
// Check the calling convention.
|
|
ImmutableCallSite CS(CI);
|
|
CallingConv::ID CC = CS.getCallingConv();
|
|
|
|
// Let SDISel handle vararg functions.
|
|
PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
|
|
FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
|
if (FTy->isVarArg())
|
|
return false;
|
|
|
|
// Handle *simple* calls for now.
|
|
MVT RetVT;
|
|
Type *RetTy = I->getType();
|
|
if (RetTy->isVoidTy())
|
|
RetVT = MVT::isVoid;
|
|
else if (!isTypeLegal(RetTy, RetVT))
|
|
return false;
|
|
|
|
// Set up the argument vectors.
|
|
SmallVector<Value *, 8> Args;
|
|
SmallVector<unsigned, 8> ArgRegs;
|
|
SmallVector<MVT, 8> ArgVTs;
|
|
SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
|
|
Args.reserve(CS.arg_size());
|
|
ArgRegs.reserve(CS.arg_size());
|
|
ArgVTs.reserve(CS.arg_size());
|
|
ArgFlags.reserve(CS.arg_size());
|
|
|
|
for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
|
|
i != e; ++i) {
|
|
// If we're lowering a memory intrinsic instead of a regular call, skip the
|
|
// last two arguments, which shouldn't be passed to the underlying function.
|
|
if (IntrMemName && e - i <= 2)
|
|
break;
|
|
|
|
unsigned Arg = getRegForValue(*i);
|
|
if (Arg == 0)
|
|
return false;
|
|
|
|
ISD::ArgFlagsTy Flags;
|
|
unsigned AttrInd = i - CS.arg_begin() + 1;
|
|
if (CS.paramHasAttr(AttrInd, Attribute::SExt))
|
|
Flags.setSExt();
|
|
if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
|
|
Flags.setZExt();
|
|
|
|
// FIXME: Only handle *easy* calls for now.
|
|
if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
|
|
CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
|
|
CS.paramHasAttr(AttrInd, Attribute::Nest) ||
|
|
CS.paramHasAttr(AttrInd, Attribute::ByVal))
|
|
return false;
|
|
|
|
MVT ArgVT;
|
|
Type *ArgTy = (*i)->getType();
|
|
if (!isTypeLegal(ArgTy, ArgVT) &&
|
|
!(ArgVT == MVT::i1 || ArgVT == MVT::i8 || ArgVT == MVT::i16))
|
|
return false;
|
|
|
|
// We don't handle vector parameters yet.
|
|
if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
|
|
return false;
|
|
|
|
unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
|
|
Flags.setOrigAlign(OriginalAlignment);
|
|
|
|
Args.push_back(*i);
|
|
ArgRegs.push_back(Arg);
|
|
ArgVTs.push_back(ArgVT);
|
|
ArgFlags.push_back(Flags);
|
|
}
|
|
|
|
// Handle the arguments now that we've gotten them.
|
|
SmallVector<unsigned, 4> RegArgs;
|
|
unsigned NumBytes;
|
|
if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
|
|
return false;
|
|
|
|
// Issue the call.
|
|
MachineInstrBuilder MIB;
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BL));
|
|
if (!IntrMemName)
|
|
MIB.addGlobalAddress(GV, 0, 0);
|
|
else
|
|
MIB.addExternalSymbol(IntrMemName, 0);
|
|
|
|
// Add implicit physical register uses to the call.
|
|
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
|
|
MIB.addReg(RegArgs[i], RegState::Implicit);
|
|
|
|
// Add a register mask with the call-preserved registers.
|
|
// Proper defs for return values will be added by setPhysRegsDeadExcept().
|
|
MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
|
|
|
|
// Finish off the call including any return values.
|
|
SmallVector<unsigned, 4> UsedRegs;
|
|
if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes))
|
|
return false;
|
|
|
|
// Set all unused physreg defs as dead.
|
|
static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
|
|
if (Alignment)
|
|
return Len / Alignment <= 4;
|
|
else
|
|
return Len < 32;
|
|
}
|
|
|
|
bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
|
|
uint64_t Len, unsigned Alignment) {
|
|
// Make sure we don't bloat code by inlining very large memcpy's.
|
|
if (!IsMemCpySmall(Len, Alignment))
|
|
return false;
|
|
|
|
int64_t UnscaledOffset = 0;
|
|
Address OrigDest = Dest;
|
|
Address OrigSrc = Src;
|
|
|
|
while (Len) {
|
|
MVT VT;
|
|
if (!Alignment || Alignment >= 8) {
|
|
if (Len >= 8)
|
|
VT = MVT::i64;
|
|
else if (Len >= 4)
|
|
VT = MVT::i32;
|
|
else if (Len >= 2)
|
|
VT = MVT::i16;
|
|
else {
|
|
VT = MVT::i8;
|
|
}
|
|
} else {
|
|
// Bound based on alignment.
|
|
if (Len >= 4 && Alignment == 4)
|
|
VT = MVT::i32;
|
|
else if (Len >= 2 && Alignment == 2)
|
|
VT = MVT::i16;
|
|
else {
|
|
VT = MVT::i8;
|
|
}
|
|
}
|
|
|
|
bool RV;
|
|
unsigned ResultReg;
|
|
RV = EmitLoad(VT, ResultReg, Src);
|
|
if (!RV)
|
|
return false;
|
|
|
|
RV = EmitStore(VT, ResultReg, Dest);
|
|
if (!RV)
|
|
return false;
|
|
|
|
int64_t Size = VT.getSizeInBits() / 8;
|
|
Len -= Size;
|
|
UnscaledOffset += Size;
|
|
|
|
// We need to recompute the unscaled offset for each iteration.
|
|
Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
|
|
Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
|
|
// FIXME: Handle more intrinsics.
|
|
switch (I.getIntrinsicID()) {
|
|
default:
|
|
return false;
|
|
case Intrinsic::memcpy:
|
|
case Intrinsic::memmove: {
|
|
const MemTransferInst &MTI = cast<MemTransferInst>(I);
|
|
// Don't handle volatile.
|
|
if (MTI.isVolatile())
|
|
return false;
|
|
|
|
// Disable inlining for memmove before calls to ComputeAddress. Otherwise,
|
|
// we would emit dead code because we don't currently handle memmoves.
|
|
bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
|
|
if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
|
|
// Small memcpy's are common enough that we want to do them without a call
|
|
// if possible.
|
|
uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
|
|
unsigned Alignment = MTI.getAlignment();
|
|
if (IsMemCpySmall(Len, Alignment)) {
|
|
Address Dest, Src;
|
|
if (!ComputeAddress(MTI.getRawDest(), Dest) ||
|
|
!ComputeAddress(MTI.getRawSource(), Src))
|
|
return false;
|
|
if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (!MTI.getLength()->getType()->isIntegerTy(64))
|
|
return false;
|
|
|
|
if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
|
|
// Fast instruction selection doesn't support the special
|
|
// address spaces.
|
|
return false;
|
|
|
|
const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
|
|
return SelectCall(&I, IntrMemName);
|
|
}
|
|
case Intrinsic::memset: {
|
|
const MemSetInst &MSI = cast<MemSetInst>(I);
|
|
// Don't handle volatile.
|
|
if (MSI.isVolatile())
|
|
return false;
|
|
|
|
if (!MSI.getLength()->getType()->isIntegerTy(64))
|
|
return false;
|
|
|
|
if (MSI.getDestAddressSpace() > 255)
|
|
// Fast instruction selection doesn't support the special
|
|
// address spaces.
|
|
return false;
|
|
|
|
return SelectCall(&I, "memset");
|
|
}
|
|
case Intrinsic::trap: {
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
|
|
.addImm(1);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectRet(const Instruction *I) {
|
|
const ReturnInst *Ret = cast<ReturnInst>(I);
|
|
const Function &F = *I->getParent()->getParent();
|
|
|
|
if (!FuncInfo.CanLowerReturn)
|
|
return false;
|
|
|
|
if (F.isVarArg())
|
|
return false;
|
|
|
|
// Build a list of return value registers.
|
|
SmallVector<unsigned, 4> RetRegs;
|
|
|
|
if (Ret->getNumOperands() > 0) {
|
|
CallingConv::ID CC = F.getCallingConv();
|
|
SmallVector<ISD::OutputArg, 4> Outs;
|
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
SmallVector<CCValAssign, 16> ValLocs;
|
|
CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
|
|
I->getContext());
|
|
CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
|
|
: RetCC_AArch64_AAPCS;
|
|
CCInfo.AnalyzeReturn(Outs, RetCC);
|
|
|
|
// Only handle a single return value for now.
|
|
if (ValLocs.size() != 1)
|
|
return false;
|
|
|
|
CCValAssign &VA = ValLocs[0];
|
|
const Value *RV = Ret->getOperand(0);
|
|
|
|
// Don't bother handling odd stuff for now.
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
return false;
|
|
// Only handle register returns for now.
|
|
if (!VA.isRegLoc())
|
|
return false;
|
|
unsigned Reg = getRegForValue(RV);
|
|
if (Reg == 0)
|
|
return false;
|
|
|
|
unsigned SrcReg = Reg + VA.getValNo();
|
|
unsigned DestReg = VA.getLocReg();
|
|
// Avoid a cross-class copy. This is very unlikely.
|
|
if (!MRI.getRegClass(SrcReg)->contains(DestReg))
|
|
return false;
|
|
|
|
EVT RVEVT = TLI.getValueType(RV->getType());
|
|
if (!RVEVT.isSimple())
|
|
return false;
|
|
|
|
// Vectors (of > 1 lane) in big endian need tricky handling.
|
|
if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
|
|
return false;
|
|
|
|
MVT RVVT = RVEVT.getSimpleVT();
|
|
if (RVVT == MVT::f128)
|
|
return false;
|
|
MVT DestVT = VA.getValVT();
|
|
// Special handling for extended integers.
|
|
if (RVVT != DestVT) {
|
|
if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
|
|
return false;
|
|
|
|
if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
|
|
return false;
|
|
|
|
bool isZExt = Outs[0].Flags.isZExt();
|
|
SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
}
|
|
|
|
// Make the copy.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
|
|
|
|
// Add register to return instruction.
|
|
RetRegs.push_back(VA.getLocReg());
|
|
}
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::RET_ReallyLR));
|
|
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
|
|
MIB.addReg(RetRegs[i], RegState::Implicit);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectTrunc(const Instruction *I) {
|
|
Type *DestTy = I->getType();
|
|
Value *Op = I->getOperand(0);
|
|
Type *SrcTy = Op->getType();
|
|
|
|
EVT SrcEVT = TLI.getValueType(SrcTy, true);
|
|
EVT DestEVT = TLI.getValueType(DestTy, true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
|
|
if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
|
|
SrcVT != MVT::i8)
|
|
return false;
|
|
if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
|
|
DestVT != MVT::i1)
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(Op);
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
// If we're truncating from i64 to a smaller non-legal type then generate an
|
|
// AND. Otherwise, we know the high bits are undefined and a truncate doesn't
|
|
// generate any code.
|
|
if (SrcVT == MVT::i64) {
|
|
uint64_t Mask = 0;
|
|
switch (DestVT.SimpleTy) {
|
|
default:
|
|
// Trunc i64 to i32 is handled by the target-independent fast-isel.
|
|
return false;
|
|
case MVT::i1:
|
|
Mask = 0x1;
|
|
break;
|
|
case MVT::i8:
|
|
Mask = 0xff;
|
|
break;
|
|
case MVT::i16:
|
|
Mask = 0xffff;
|
|
break;
|
|
}
|
|
// Issue an extract_subreg to get the lower 32-bits.
|
|
unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
|
|
AArch64::sub_32);
|
|
MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
|
|
// Create the AND instruction which performs the actual truncation.
|
|
unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
|
ANDReg)
|
|
.addReg(Reg32)
|
|
.addImm(AArch64_AM::encodeLogicalImmediate(Mask, 32));
|
|
SrcReg = ANDReg;
|
|
}
|
|
|
|
UpdateValueMap(I, SrcReg);
|
|
return true;
|
|
}
|
|
|
|
unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
|
|
assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
|
|
DestVT == MVT::i64) &&
|
|
"Unexpected value type.");
|
|
// Handle i8 and i16 as i32.
|
|
if (DestVT == MVT::i8 || DestVT == MVT::i16)
|
|
DestVT = MVT::i32;
|
|
|
|
if (isZExt) {
|
|
MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
|
|
unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
|
|
ResultReg)
|
|
.addReg(SrcReg)
|
|
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
|
|
|
|
if (DestVT == MVT::i64) {
|
|
// We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
|
|
// upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
|
|
unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), Reg64)
|
|
.addImm(0)
|
|
.addReg(ResultReg)
|
|
.addImm(AArch64::sub_32);
|
|
ResultReg = Reg64;
|
|
}
|
|
return ResultReg;
|
|
} else {
|
|
if (DestVT == MVT::i64) {
|
|
// FIXME: We're SExt i1 to i64.
|
|
return 0;
|
|
}
|
|
unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
|
|
ResultReg)
|
|
.addReg(SrcReg)
|
|
.addImm(0)
|
|
.addImm(0);
|
|
return ResultReg;
|
|
}
|
|
}
|
|
|
|
unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
bool isZExt) {
|
|
assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
|
|
unsigned Opc;
|
|
unsigned Imm = 0;
|
|
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return 0;
|
|
case MVT::i1:
|
|
return Emiti1Ext(SrcReg, DestVT, isZExt);
|
|
case MVT::i8:
|
|
if (DestVT == MVT::i64)
|
|
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
|
else
|
|
Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
|
Imm = 7;
|
|
break;
|
|
case MVT::i16:
|
|
if (DestVT == MVT::i64)
|
|
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
|
else
|
|
Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
|
Imm = 15;
|
|
break;
|
|
case MVT::i32:
|
|
assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
|
|
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
|
Imm = 31;
|
|
break;
|
|
}
|
|
|
|
// Handle i8 and i16 as i32.
|
|
if (DestVT == MVT::i8 || DestVT == MVT::i16)
|
|
DestVT = MVT::i32;
|
|
else if (DestVT == MVT::i64) {
|
|
unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), Src64)
|
|
.addImm(0)
|
|
.addReg(SrcReg)
|
|
.addImm(AArch64::sub_32);
|
|
SrcReg = Src64;
|
|
}
|
|
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
.addReg(SrcReg)
|
|
.addImm(0)
|
|
.addImm(Imm);
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
|
// On ARM, in general, integer casts don't involve legal types; this code
|
|
// handles promotable integers. The high bits for a type smaller than
|
|
// the register size are assumed to be undefined.
|
|
Type *DestTy = I->getType();
|
|
Value *Src = I->getOperand(0);
|
|
Type *SrcTy = Src->getType();
|
|
|
|
bool isZExt = isa<ZExtInst>(I);
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
EVT SrcEVT = TLI.getValueType(SrcTy, true);
|
|
EVT DestEVT = TLI.getValueType(DestTy, true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
|
|
if (ResultReg == 0)
|
|
return false;
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
|
|
EVT DestEVT = TLI.getValueType(I->getType(), true);
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
if (DestVT != MVT::i64 && DestVT != MVT::i32)
|
|
return false;
|
|
|
|
unsigned DivOpc;
|
|
bool is64bit = (DestVT == MVT::i64);
|
|
switch (ISDOpcode) {
|
|
default:
|
|
return false;
|
|
case ISD::SREM:
|
|
DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
|
|
break;
|
|
case ISD::UREM:
|
|
DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
|
|
break;
|
|
}
|
|
unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
|
|
unsigned Src0Reg = getRegForValue(I->getOperand(0));
|
|
if (!Src0Reg)
|
|
return false;
|
|
|
|
unsigned Src1Reg = getRegForValue(I->getOperand(1));
|
|
if (!Src1Reg)
|
|
return false;
|
|
|
|
unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
|
|
.addReg(Src0Reg)
|
|
.addReg(Src1Reg);
|
|
// The remainder is computed as numerator - (quotient * denominator) using the
|
|
// MSUB instruction.
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
|
|
.addReg(QuotReg)
|
|
.addReg(Src1Reg)
|
|
.addReg(Src0Reg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectMul(const Instruction *I) {
|
|
EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
|
|
// Must be simple value type. Don't handle vectors.
|
|
if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
|
|
SrcVT != MVT::i8)
|
|
return false;
|
|
|
|
unsigned Opc;
|
|
unsigned ZReg;
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
ZReg = AArch64::WZR;
|
|
Opc = AArch64::MADDWrrr;
|
|
break;
|
|
case MVT::i64:
|
|
ZReg = AArch64::XZR;
|
|
Opc = AArch64::MADDXrrr;
|
|
break;
|
|
}
|
|
|
|
unsigned Src0Reg = getRegForValue(I->getOperand(0));
|
|
if (!Src0Reg)
|
|
return false;
|
|
|
|
unsigned Src1Reg = getRegForValue(I->getOperand(1));
|
|
if (!Src1Reg)
|
|
return false;
|
|
|
|
// Create the base instruction, then add the operands.
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(SrcVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
.addReg(Src0Reg)
|
|
.addReg(Src1Reg)
|
|
.addReg(ZReg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
|
|
switch (I->getOpcode()) {
|
|
default:
|
|
break;
|
|
case Instruction::Load:
|
|
return SelectLoad(I);
|
|
case Instruction::Store:
|
|
return SelectStore(I);
|
|
case Instruction::Br:
|
|
return SelectBranch(I);
|
|
case Instruction::IndirectBr:
|
|
return SelectIndirectBr(I);
|
|
case Instruction::FCmp:
|
|
case Instruction::ICmp:
|
|
return SelectCmp(I);
|
|
case Instruction::Select:
|
|
return SelectSelect(I);
|
|
case Instruction::FPExt:
|
|
return SelectFPExt(I);
|
|
case Instruction::FPTrunc:
|
|
return SelectFPTrunc(I);
|
|
case Instruction::FPToSI:
|
|
return SelectFPToInt(I, /*Signed=*/true);
|
|
case Instruction::FPToUI:
|
|
return SelectFPToInt(I, /*Signed=*/false);
|
|
case Instruction::SIToFP:
|
|
return SelectIntToFP(I, /*Signed=*/true);
|
|
case Instruction::UIToFP:
|
|
return SelectIntToFP(I, /*Signed=*/false);
|
|
case Instruction::SRem:
|
|
return SelectRem(I, ISD::SREM);
|
|
case Instruction::URem:
|
|
return SelectRem(I, ISD::UREM);
|
|
case Instruction::Call:
|
|
if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
|
|
return SelectIntrinsicCall(*II);
|
|
return SelectCall(I);
|
|
case Instruction::Ret:
|
|
return SelectRet(I);
|
|
case Instruction::Trunc:
|
|
return SelectTrunc(I);
|
|
case Instruction::ZExt:
|
|
case Instruction::SExt:
|
|
return SelectIntExt(I);
|
|
case Instruction::Mul:
|
|
// FIXME: This really should be handled by the target-independent selector.
|
|
return SelectMul(I);
|
|
}
|
|
return false;
|
|
// Silence warnings.
|
|
(void)&CC_AArch64_DarwinPCS_VarArg;
|
|
}
|
|
|
|
namespace llvm {
|
|
llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) {
|
|
return new AArch64FastISel(funcInfo, libInfo);
|
|
}
|
|
}
|