Rafael Espindola 50b935707f Write section and section table entries in the same order. ... We had two different orders, which has no value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235004 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-15 13:07:47 +00:00
..
Analysis	Re-apply r234898 and fix tests.	2015-04-15 06:24:07 +00:00
AsmParser	Remove empty non-virtual destructors or mark them =default when non-public	2015-04-11 15:32:26 +00:00
Bitcode	Revert "Verify sizes when trying to read a VBR"	2015-04-15 11:10:17 +00:00
CodeGen	Change range-based for-loops to be -Wrange-loop-analysis clean.	2015-04-15 01:21:15 +00:00
DebugInfo
ExecutionEngine	[RuntimeDyld] Add casts to make delta computation 64-bit.	2015-04-15 04:46:01 +00:00
Fuzzer
IR	uselistorder: Remove the global bits	2015-04-15 03:14:06 +00:00
IRReader
LineEditor
Linker	DebugInfo: Gut DISubprogram and DILexicalBlock*	2015-04-14 03:40:37 +00:00
LTO	uselistorder: Remove the global bits	2015-04-15 03:14:06 +00:00
MC	Write section and section table entries in the same order.	2015-04-15 13:07:47 +00:00
Object	Change range-based for-loops to be -Wrange-loop-analysis clean.	2015-04-15 01:21:15 +00:00
Option
Passes
ProfileData
Support	Fix lib\support\Windows/TimeValue.inc(48): warning C4189:	2015-04-15 07:45:52 +00:00
TableGen	Remove empty non-virtual destructors or mark them =default when non-public	2015-04-11 15:32:26 +00:00
Target	[msp430] Only support the 'm' inline assembly memory constraint. NFC.	2015-04-15 12:51:28 +00:00
Transforms	Change range-based for-loops to be -Wrange-loop-analysis clean.	2015-04-15 01:21:15 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile