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1d09d56fe1
This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
3.9 KiB
Plaintext
147 lines
3.9 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random notes about and ideas for the SystemZ backend.
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//===---------------------------------------------------------------------===//
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The initial backend is deliberately restricted to z10. We should add support
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for later architectures at some point.
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--
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SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
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inline asm memory constraints; it doesn't get to see the original constraint.
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This means that it must conservatively treat all inline asm constraints
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as the most restricted type, "R".
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--
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If an inline asm ties an i32 "r" result to an i64 input, the input
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will be treated as an i32, leaving the upper bits uninitialised.
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For example:
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define void @f4(i32 *%dst) {
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%val = call i32 asm "blah $0", "=r,0" (i64 103)
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store i32 %val, i32 *%dst
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ret void
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}
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from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
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to load 103. This seems to be a general target-independent problem.
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--
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The tuning of the choice between Load Address (LA) and addition in
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SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on
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performance measurements.
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--
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There is no scheduling support.
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--
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We don't use the Branch on Count or Branch on Index families of instruction.
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--
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We don't use the condition code results of anything except comparisons.
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Implementing this may need something more finely grained than the z_cmp
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and z_ucmp that we have now. It might (or might not) also be useful to
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have a mask of "don't care" values in conditional branches. For example,
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integer comparisons never set CC to 3, so the bottom bit of the CC mask
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isn't particularly relevant. JNLH and JE are equally good for testing
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equality after an integer comparison, etc.
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--
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We don't optimize string and block memory operations.
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--
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We don't take full advantage of builtins like fabsl because the calling
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conventions require f128s to be returned by invisible reference.
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--
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DAGCombiner can detect integer absolute, but there's not yet an associated
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ISD opcode. We could add one and implement it using Load Positive.
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Negated absolutes could use Load Negative.
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--
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DAGCombiner doesn't yet fold truncations of extended loads. Functions like:
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unsigned long f (unsigned long x, unsigned short *y)
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{
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return (x << 32) | *y;
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}
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therefore end up as:
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sllg %r2, %r2, 32
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llgh %r0, 0(%r3)
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lr %r2, %r0
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br %r14
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but truncating the load would give:
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sllg %r2, %r2, 32
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lh %r2, 0(%r3)
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br %r14
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--
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Functions like:
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define i64 @f1(i64 %a) {
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%and = and i64 %a, 1
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ret i64 %and
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}
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ought to be implemented as:
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lhi %r0, 1
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ngr %r2, %r0
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br %r14
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but two-address optimisations reverse the order of the AND and force:
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lhi %r0, 1
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ngr %r0, %r2
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lgr %r2, %r0
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br %r14
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CodeGen/SystemZ/and-04.ll has several examples of this.
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--
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Out-of-range displacements are usually handled by loading the full
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address into a register. In many cases it would be better to create
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an anchor point instead. E.g. for:
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define void @f4a(i128 *%aptr, i64 %base) {
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%addr = add i64 %base, 524288
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%bptr = inttoptr i64 %addr to i128 *
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%a = load volatile i128 *%aptr
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%b = load i128 *%bptr
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%add = add i128 %a, %b
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store i128 %add, i128 *%aptr
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ret void
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}
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(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
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into separate registers, rather than using %base+524288 as a base for both.
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--
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Dynamic stack allocations round the size to 8 bytes and then allocate
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that rounded amount. It would be simpler to subtract the unrounded
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size from the copy of the stack pointer and then align the result.
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See CodeGen/SystemZ/alloca-01.ll for an example.
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--
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Atomic loads and stores use the default compare-and-swap based implementation.
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This is probably much too conservative in practice, and the overhead is
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especially bad for 8- and 16-bit accesses.
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