llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-19 20:34:38 +00:00

History

Quentin Colombet 50d4008b47 [LSR] Canonicalize reg1 + ... + regN into reg1 + ... + 1*regN.

This commit introduces a canonical representation for the formulae.
Basically, as soon as a formula has more that one base register, the scaled
register field is used for one of them. The register put into the scaled
register is preferably a loop variant.
The commit refactors how the formulae are built in order to produce such
representation.
This yields a more accurate, but still perfectible, cost model.

<rdar://problem/16731508>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209230 91177308-0d34-0410-b5e6-96231b3b80d8

2014-05-20 19:25:04 +00:00

AArch64

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ARM

SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bswap not.

2014-05-19 13:12:38 +00:00

ARM64

[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.

2014-05-19 22:59:51 +00:00

CPP

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Generic