mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-10 01:10:48 +00:00
38d5e1c36d
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.3 KiB
C++
68 lines
2.3 KiB
C++
//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "AMDGPURegisterInfo.h"
|
|
#include "AMDGPUTargetMachine.h"
|
|
|
|
using namespace llvm;
|
|
|
|
AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm)
|
|
: AMDGPUGenRegisterInfo(0),
|
|
TM(tm)
|
|
{ }
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Function handling callbacks - Functions are a seldom used feature of GPUS, so
|
|
// they are not supported at this time.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
|
|
|
|
const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
|
|
const {
|
|
return &CalleeSavedReg;
|
|
}
|
|
|
|
void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|
int SPAdj,
|
|
unsigned FIOperandNum,
|
|
RegScavenger *RS) const {
|
|
assert(!"Subroutines not supported yet");
|
|
}
|
|
|
|
unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
assert(!"Subroutines not supported yet");
|
|
return 0;
|
|
}
|
|
|
|
unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
|
|
static const unsigned SubRegs[] = {
|
|
AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
|
|
AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
|
|
AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
|
|
AMDGPU::sub15
|
|
};
|
|
|
|
assert (Channel < array_lengthof(SubRegs));
|
|
return SubRegs[Channel];
|
|
}
|
|
|
|
unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
|
|
|
|
return getSubRegFromChannel(IndirectIndex);
|
|
}
|
|
|
|
#define GET_REGINFO_TARGET_DESC
|
|
#include "AMDGPUGenRegisterInfo.inc"
|