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https://github.com/c64scene-ar/llvm-6502.git
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055b0310f8
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
270 lines
9.5 KiB
C++
270 lines
9.5 KiB
C++
//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMINSTRUCTIONINFO_H
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#define ARMINSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARM.h"
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namespace llvm {
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class ARMSubtarget;
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/// ARMII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace ARMII {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction Flags.
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//===------------------------------------------------------------------===//
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// This four-bit field describes the addressing mode used.
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AddrModeMask = 0xf,
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AddrModeNone = 0,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrModeT1_1 = 6,
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AddrModeT1_2 = 7,
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AddrModeT1_4 = 8,
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AddrModeT1_s = 9, // i8 * 4 for pc and sp relative data
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AddrModeT2_i12= 10,
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AddrModeT2_i8 = 11,
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AddrModeT2_so = 12,
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AddrModeT2_pc = 13, // +/- i12 for pc relative data
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// Size* - Flags to keep track of the size of an instruction.
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SizeShift = 4,
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SizeMask = 7 << SizeShift,
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SizeSpecial = 1, // 0 byte pseudo or special case.
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Size8Bytes = 2,
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Size4Bytes = 3,
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Size2Bytes = 4,
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// IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
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// and store ops
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IndexModeShift = 7,
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IndexModeMask = 3 << IndexModeShift,
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IndexModePre = 1,
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IndexModePost = 2,
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//===------------------------------------------------------------------===//
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// Misc flags.
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// UnaryDP - Indicates this is a unary data processing instruction, i.e.
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// it doesn't have a Rn operand.
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UnaryDP = 1 << 9,
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//===------------------------------------------------------------------===//
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// Instruction encoding formats.
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//
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FormShift = 10,
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FormMask = 0x1f << FormShift,
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// Pseudo instructions
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Pseudo = 0 << FormShift,
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// Multiply instructions
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MulFrm = 1 << FormShift,
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// Branch instructions
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BrFrm = 2 << FormShift,
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BrMiscFrm = 3 << FormShift,
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// Data Processing instructions
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DPFrm = 4 << FormShift,
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DPSoRegFrm = 5 << FormShift,
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// Load and Store
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LdFrm = 6 << FormShift,
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StFrm = 7 << FormShift,
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LdMiscFrm = 8 << FormShift,
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StMiscFrm = 9 << FormShift,
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LdStMulFrm = 10 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMiscFrm = 11 << FormShift,
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// Extend instructions
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ExtFrm = 12 << FormShift,
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// VFP formats
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VFPUnaryFrm = 13 << FormShift,
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VFPBinaryFrm = 14 << FormShift,
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VFPConv1Frm = 15 << FormShift,
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VFPConv2Frm = 16 << FormShift,
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VFPConv3Frm = 17 << FormShift,
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VFPConv4Frm = 18 << FormShift,
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VFPConv5Frm = 19 << FormShift,
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VFPLdStFrm = 20 << FormShift,
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VFPLdStMulFrm = 21 << FormShift,
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VFPMiscFrm = 22 << FormShift,
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// Thumb format
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ThumbFrm = 23 << FormShift,
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// NEON format
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NEONFrm = 24 << FormShift,
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NEONGetLnFrm = 25 << FormShift,
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NEONSetLnFrm = 26 << FormShift,
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NEONDupFrm = 27 << FormShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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M_BitShift = 5,
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ShiftImmShift = 5,
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ShiftShift = 7,
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N_BitShift = 7,
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ImmHiShift = 8,
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SoRotImmShift = 8,
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RegRsShift = 8,
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ExtRotImmShift = 10,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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S_BitShift = 20,
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W_BitShift = 21,
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AM3_I_BitShift = 22,
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D_BitShift = 22,
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U_BitShift = 23,
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P_BitShift = 24,
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I_BitShift = 25,
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CondShift = 28
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};
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}
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class ARMBaseInstrInfo : public TargetInstrInfoImpl {
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protected:
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// Can be only subclassed.
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explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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public:
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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// Predication support.
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virtual bool isPredicated(const MachineInstr *MI) const;
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ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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int PIdx = MI->findFirstPredOperandIdx();
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return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
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: ARMCC::AL;
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}
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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};
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class ARMInstrInfo : public ARMBaseInstrInfo {
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ARMRegisterInfo RI;
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public:
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explicit ARMInstrInfo(const ARMSubtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
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/// Return true if the instruction is a register to register move and return
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/// the source and dest operands and their sub-register indices by reference.
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virtual bool isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const;
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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virtual bool canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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};
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}
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#endif
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