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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28229 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
2.0 KiB
C++
53 lines
2.0 KiB
C++
//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Constant.h"
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#include "llvm/DerivedTypes.h"
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using namespace llvm;
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namespace llvm {
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// External object describing the machine instructions Initialized only when
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// the TargetMachine class is created and reset when that class is destroyed.
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//
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// FIXME: UGLY SPARCV9 HACK!
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const TargetInstrDescriptor* TargetInstrDescriptors = 0;
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}
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TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
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unsigned numOpcodes)
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: desc(Desc), NumOpcodes(numOpcodes) {
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// FIXME: TargetInstrDescriptors should not be global
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assert(TargetInstrDescriptors == NULL && desc != NULL
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&& "TargetMachine data structure corrupt; maybe you tried to create another TargetMachine? (only one may exist in a program)");
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TargetInstrDescriptors = desc; // initialize global variable
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}
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TargetInstrInfo::~TargetInstrInfo() {
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TargetInstrDescriptors = NULL; // reset global variable
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}
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// commuteInstruction - The default implementation of this method just exchanges
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// operand 1 and 2.
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MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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return MI;
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}
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