mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c24cb3551e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
2.5 KiB
LLVM
93 lines
2.5 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vceqi8:
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;CHECK: vceq.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vceqi16:
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;CHECK: vceq.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vceqi32:
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;CHECK: vceq.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vceqf32:
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;CHECK: vceq.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vceqQi8:
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;CHECK: vceq.i8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vceqQi16:
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;CHECK: vceq.i16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vceqQi32:
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;CHECK: vceq.i32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vceqQf32:
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;CHECK: vceq.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
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;CHECK: vceqi8Z:
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;CHECK-NOT: vmov
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;CHECK-NOT: vmvn
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;CHECK: vceq.i8
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%tmp1 = load <8 x i8>* %A
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%tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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