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The convention used to specify the PowerPC ISA is that bits are numbered in reverse order (0 is the index of the high bit). To support this "little endian" encoding convention, CodeEmitterGen will reverse the bit numberings prior to generating the encoding tables. In order to generate a disassembler, FixedLenDecoderEmitter needs to do the same. This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget (where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This is prep work for disassembly support in the PPC backend (which is the only in-tree user of this little-endian encoding support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197532 91177308-0d34-0410-b5e6-96231b3b80d8
216 lines
6.7 KiB
C++
216 lines
6.7 KiB
C++
//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines wrappers for the Target class and related global
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// functionality. This makes it easier to access the data and provides a single
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// place that needs to check it for validity. All of these classes abort
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// on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_TARGET_H
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#define CODEGEN_TARGET_H
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#include "CodeGenInstruction.h"
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#include "CodeGenRegisters.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Record.h"
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#include <algorithm>
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namespace llvm {
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struct CodeGenRegister;
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class CodeGenSchedModels;
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class CodeGenTarget;
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// SelectionDAG node properties.
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// SDNPMemOperand: indicates that a node touches memory and therefore must
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// have an associated memory operand that describes the access.
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enum SDNP {
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SDNPCommutative,
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SDNPAssociative,
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SDNPHasChain,
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SDNPOutGlue,
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SDNPInGlue,
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SDNPOptInGlue,
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SDNPMayLoad,
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SDNPMayStore,
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SDNPSideEffect,
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SDNPMemOperand,
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SDNPVariadic,
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SDNPWantRoot,
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SDNPWantParent
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};
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType getValueType(Record *Rec);
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std::string getName(MVT::SimpleValueType T);
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std::string getEnumName(MVT::SimpleValueType T);
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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std::string getQualifiedName(const Record *R);
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/// CodeGenTarget - This class corresponds to the Target class in the .td files.
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///
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class CodeGenTarget {
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RecordKeeper &Records;
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Record *TargetRec;
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mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
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mutable CodeGenRegBank *RegBank;
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mutable std::vector<Record*> RegAltNameIndices;
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mutable SmallVector<MVT::SimpleValueType, 8> LegalValueTypes;
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void ReadRegAltNameIndices() const;
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void ReadInstructions() const;
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void ReadLegalValueTypes() const;
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mutable CodeGenSchedModels *SchedModels;
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mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
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public:
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CodeGenTarget(RecordKeeper &Records);
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~CodeGenTarget();
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Record *getTargetRecord() const { return TargetRec; }
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const std::string &getName() const;
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/// getInstNamespace - Return the target-specific instruction namespace.
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///
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std::string getInstNamespace() const;
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/// getInstructionSet - Return the InstructionSet object.
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///
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Record *getInstructionSet() const;
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *getAsmParser() const;
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/// getAsmParserVariant - Return the AssmblyParserVariant definition for
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/// this target.
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///
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Record *getAsmParserVariant(unsigned i) const;
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/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
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/// available for this target.
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///
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unsigned getAsmParserVariantCount() const;
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *getAsmWriter() const;
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/// getRegBank - Return the register bank description.
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CodeGenRegBank &getRegBank() const;
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *getRegisterByName(StringRef Name) const;
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const std::vector<Record*> &getRegAltNameIndices() const {
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if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
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return RegAltNameIndices;
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}
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const CodeGenRegisterClass &getRegisterClass(Record *R) const {
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return *getRegBank().getRegClass(R);
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}
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/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
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/// specified physical register.
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std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
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ArrayRef<MVT::SimpleValueType> getLegalValueTypes() const {
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if (LegalValueTypes.empty()) ReadLegalValueTypes();
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return LegalValueTypes;
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}
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/// isLegalValueType - Return true if the specified value type is natively
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/// supported by the target (i.e. there are registers that directly hold it).
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bool isLegalValueType(MVT::SimpleValueType VT) const {
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ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes();
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for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
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if (LegalVTs[i] == VT) return true;
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return false;
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}
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CodeGenSchedModels &getSchedModels() const;
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private:
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DenseMap<const Record*, CodeGenInstruction*> &getInstructions() const {
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if (Instructions.empty()) ReadInstructions();
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return Instructions;
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}
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public:
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CodeGenInstruction &getInstruction(const Record *InstRec) const {
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if (Instructions.empty()) ReadInstructions();
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DenseMap<const Record*, CodeGenInstruction*>::iterator I =
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Instructions.find(InstRec);
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assert(I != Instructions.end() && "Not an instruction");
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return *I->second;
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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const std::vector<const CodeGenInstruction*> &
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getInstructionsByEnumValue() const {
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if (InstrsByEnum.empty()) ComputeInstrsByEnum();
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return InstrsByEnum;
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}
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typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
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inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
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inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
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/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
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///
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bool isLittleEndianEncoding() const;
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/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
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/// encodings, reverse the bit order of all instructions.
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void reverseBitsForLittleEndianEncoding();
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/// guessInstructionProperties - should we just guess unset instruction
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/// properties?
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bool guessInstructionProperties() const;
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private:
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void ComputeInstrsByEnum() const;
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};
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/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
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/// tablegen class in TargetSelectionDAG.td
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class ComplexPattern {
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MVT::SimpleValueType Ty;
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unsigned NumOperands;
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std::string SelectFunc;
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std::vector<Record*> RootNodes;
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unsigned Properties; // Node properties
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public:
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ComplexPattern() : NumOperands(0) {}
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ComplexPattern(Record *R);
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MVT::SimpleValueType getValueType() const { return Ty; }
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unsigned getNumOperands() const { return NumOperands; }
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const std::string &getSelectFunc() const { return SelectFunc; }
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const std::vector<Record*> &getRootNodes() const {
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return RootNodes;
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}
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bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
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};
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} // End llvm namespace
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#endif
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