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https://github.com/c64scene-ar/llvm-6502.git
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72062f5744
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.5 KiB
C++
79 lines
2.5 KiB
C++
//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeAArch64Target() {
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RegisterTargetMachine<AArch64TargetMachine> X(TheAArch64Target);
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}
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AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS),
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InstrInfo(Subtarget),
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DL("e-p:64:64-i64:64:64-i128:128:128-s0:32:32-f128:128:128-n32:64-S128"),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget) {
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}
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namespace {
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/// AArch64 Code Generator Pass Configuration Options.
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class AArch64PassConfig : public TargetPassConfig {
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public:
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AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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AArch64TargetMachine &getAArch64TargetMachine() const {
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return getTM<AArch64TargetMachine>();
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}
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const AArch64Subtarget &getAArch64Subtarget() const {
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return *getAArch64TargetMachine().getSubtargetImpl();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AArch64PassConfig(this, PM);
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}
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bool AArch64PassConfig::addPreEmitPass() {
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addPass(&UnpackMachineBundlesID);
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addPass(createAArch64ConstantIslandPass());
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return true;
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}
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bool AArch64PassConfig::addInstSelector() {
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addPass(createAArch64ISelDAG(getAArch64TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses.
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if (getAArch64Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
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addPass(createAArch64CleanupLocalDynamicTLSPass());
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return false;
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}
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