mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
5bac8f9b95
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231524 91177308-0d34-0410-b5e6-96231b3b80d8
326 lines
11 KiB
LLVM
326 lines
11 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
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; RUN: llc < %s -march=x86-64 -mattr=avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
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; RUN: llc < %s -march=x86-64 -mattr=avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
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; Verify that we correctly fold horizontal binop even in the presence of UNDEFs.
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define <4 x float> @test1_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %a, i32 2
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%vecext3 = extractelement <4 x float> %a, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
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%vecext10 = extractelement <4 x float> %b, i32 2
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%vecext11 = extractelement <4 x float> %b, i32 3
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%add12 = fadd float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit5, float %add12, i32 3
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ret <4 x float> %vecinit13
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}
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; CHECK-LABEL: test1_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NEXT: ret
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define <4 x float> @test2_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext6 = extractelement <4 x float> %b, i32 0
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%vecext7 = extractelement <4 x float> %b, i32 1
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%add8 = fadd float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit, float %add8, i32 2
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%vecext10 = extractelement <4 x float> %b, i32 2
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%vecext11 = extractelement <4 x float> %b, i32 3
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%add12 = fadd float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
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ret <4 x float> %vecinit13
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}
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; CHECK-LABEL: test2_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NEXT: ret
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define <4 x float> @test3_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %a, i32 2
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%vecext3 = extractelement <4 x float> %a, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
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%vecext6 = extractelement <4 x float> %b, i32 0
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%vecext7 = extractelement <4 x float> %b, i32 1
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%add8 = fadd float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
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ret <4 x float> %vecinit9
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}
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; CHECK-LABEL: test3_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NEXT: ret
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define <4 x float> @test4_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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ret <4 x float> %vecinit
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}
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; CHECK-LABEL: test4_undef
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; CHECK-NOT: haddps
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; CHECK: ret
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define <2 x double> @test5_undef(<2 x double> %a, <2 x double> %b) {
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%vecext = extractelement <2 x double> %a, i32 0
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%vecext1 = extractelement <2 x double> %a, i32 1
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%add = fadd double %vecext, %vecext1
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%vecinit = insertelement <2 x double> undef, double %add, i32 0
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ret <2 x double> %vecinit
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}
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; CHECK-LABEL: test5_undef
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; CHECK-NOT: haddpd
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; CHECK: ret
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define <4 x float> @test6_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %a, i32 2
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%vecext3 = extractelement <4 x float> %a, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
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ret <4 x float> %vecinit5
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}
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; CHECK-LABEL: test6_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NEXT: ret
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define <4 x float> @test7_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %b, i32 0
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%vecext1 = extractelement <4 x float> %b, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 2
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%vecext2 = extractelement <4 x float> %b, i32 2
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%vecext3 = extractelement <4 x float> %b, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 3
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ret <4 x float> %vecinit5
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}
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; CHECK-LABEL: test7_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NEXT: ret
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define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %a, i32 2
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%vecext3 = extractelement <4 x float> %a, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 2
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ret <4 x float> %vecinit5
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}
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; CHECK-LABEL: test8_undef
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; CHECK-NOT: haddps
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; CHECK: ret
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define <4 x float> @test9_undef(<4 x float> %a, <4 x float> %b) {
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %b, i32 2
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%vecext3 = extractelement <4 x float> %b, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 3
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ret <4 x float> %vecinit5
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}
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; CHECK-LABEL: test9_undef
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; CHECK: haddps
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; CHECK-NEXT: ret
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define <8 x float> @test10_undef(<8 x float> %a, <8 x float> %b) {
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%vecext = extractelement <8 x float> %a, i32 0
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%vecext1 = extractelement <8 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <8 x float> undef, float %add, i32 0
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%vecext2 = extractelement <8 x float> %b, i32 2
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%vecext3 = extractelement <8 x float> %b, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 3
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ret <8 x float> %vecinit5
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}
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; CHECK-LABEL: test10_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NOT: haddps
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; CHECK: ret
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define <8 x float> @test11_undef(<8 x float> %a, <8 x float> %b) {
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%vecext = extractelement <8 x float> %a, i32 0
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%vecext1 = extractelement <8 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <8 x float> undef, float %add, i32 0
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%vecext2 = extractelement <8 x float> %b, i32 4
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%vecext3 = extractelement <8 x float> %b, i32 5
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 6
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ret <8 x float> %vecinit5
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}
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; CHECK-LABEL: test11_undef
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; SSE-NOT: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK: ret
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define <8 x float> @test12_undef(<8 x float> %a, <8 x float> %b) {
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%vecext = extractelement <8 x float> %a, i32 0
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%vecext1 = extractelement <8 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <8 x float> undef, float %add, i32 0
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%vecext2 = extractelement <8 x float> %a, i32 2
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%vecext3 = extractelement <8 x float> %a, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 1
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ret <8 x float> %vecinit5
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}
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; CHECK-LABEL: test12_undef
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; SSE: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NOT: haddps
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; CHECK: ret
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define <8 x float> @test13_undef(<8 x float> %a, <8 x float> %b) {
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%vecext = extractelement <8 x float> %a, i32 0
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%vecext1 = extractelement <8 x float> %a, i32 1
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%add1 = fadd float %vecext, %vecext1
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%vecinit1 = insertelement <8 x float> undef, float %add1, i32 0
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%vecext2 = extractelement <8 x float> %a, i32 2
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%vecext3 = extractelement <8 x float> %a, i32 3
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%add2 = fadd float %vecext2, %vecext3
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%vecinit2 = insertelement <8 x float> %vecinit1, float %add2, i32 1
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%vecext4 = extractelement <8 x float> %a, i32 4
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%vecext5 = extractelement <8 x float> %a, i32 5
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%add3 = fadd float %vecext4, %vecext5
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%vecinit3 = insertelement <8 x float> %vecinit2, float %add3, i32 2
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%vecext6 = extractelement <8 x float> %a, i32 6
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%vecext7 = extractelement <8 x float> %a, i32 7
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%add4 = fadd float %vecext6, %vecext7
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%vecinit4 = insertelement <8 x float> %vecinit3, float %add4, i32 3
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ret <8 x float> %vecinit4
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}
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; CHECK-LABEL: test13_undef
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; SSE: haddps
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; SSE-NOT: haddps
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; AVX: vhaddps
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; AVX2: vhaddps
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; CHECK-NOT: haddps
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; CHECK: ret
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define <8 x i32> @test14_undef(<8 x i32> %a, <8 x i32> %b) {
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <8 x i32> %b, i32 2
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%vecext3 = extractelement <8 x i32> %b, i32 3
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 3
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ret <8 x i32> %vecinit5
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}
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; CHECK-LABEL: test14_undef
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; SSE: phaddd
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; AVX: vphaddd
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; AVX2: vphaddd
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; CHECK-NOT: phaddd
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; CHECK: ret
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; On AVX2, the following sequence can be folded into a single horizontal add.
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; If the Subtarget doesn't support AVX2, then we avoid emitting two packed
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; integer horizontal adds instead of two scalar adds followed by vector inserts.
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define <8 x i32> @test15_undef(<8 x i32> %a, <8 x i32> %b) {
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <8 x i32> %b, i32 4
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%vecext3 = extractelement <8 x i32> %b, i32 5
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 6
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ret <8 x i32> %vecinit5
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}
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; CHECK-LABEL: test15_undef
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; SSE-NOT: phaddd
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; AVX-NOT: vphaddd
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; AVX2: vphaddd
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; CHECK: ret
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define <8 x i32> @test16_undef(<8 x i32> %a, <8 x i32> %b) {
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <8 x i32> %a, i32 2
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%vecext3 = extractelement <8 x i32> %a, i32 3
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 1
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ret <8 x i32> %vecinit5
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}
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; CHECK-LABEL: test16_undef
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; SSE: phaddd
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; AVX: vphaddd
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; AVX2: vphaddd
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; CHECK-NOT: haddps
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; CHECK: ret
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define <8 x i32> @test17_undef(<8 x i32> %a, <8 x i32> %b) {
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add1 = add i32 %vecext, %vecext1
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%vecinit1 = insertelement <8 x i32> undef, i32 %add1, i32 0
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%vecext2 = extractelement <8 x i32> %a, i32 2
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%vecext3 = extractelement <8 x i32> %a, i32 3
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%add2 = add i32 %vecext2, %vecext3
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%vecinit2 = insertelement <8 x i32> %vecinit1, i32 %add2, i32 1
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%vecext4 = extractelement <8 x i32> %a, i32 4
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%vecext5 = extractelement <8 x i32> %a, i32 5
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%add3 = add i32 %vecext4, %vecext5
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%vecinit3 = insertelement <8 x i32> %vecinit2, i32 %add3, i32 2
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%vecext6 = extractelement <8 x i32> %a, i32 6
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%vecext7 = extractelement <8 x i32> %a, i32 7
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%add4 = add i32 %vecext6, %vecext7
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%vecinit4 = insertelement <8 x i32> %vecinit3, i32 %add4, i32 3
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ret <8 x i32> %vecinit4
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}
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; CHECK-LABEL: test17_undef
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; SSE: phaddd
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; AVX: vphaddd
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; AVX2: vphaddd
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; CHECK-NOT: haddps
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; CHECK: ret
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