mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
392 lines
7.6 KiB
LLVM
392 lines
7.6 KiB
LLVM
; Test the basic functionality of integer element promotions of different types.
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; This tests checks passing of arguments, loading and storing to memory and
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; basic arithmetic.
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; RUN: llc -march=x86 < %s > /dev/null
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; RUN: llc -march=x86-64 < %s > /dev/null
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define <1 x i8> @test_1xi8(<1 x i8> %x, <1 x i8>* %b) {
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%bb = load <1 x i8>, <1 x i8>* %b
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%tt = xor <1 x i8> %x, %bb
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store <1 x i8> %tt, <1 x i8>* %b
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br label %next
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next:
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ret <1 x i8> %tt
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}
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define <1 x i16> @test_1xi16(<1 x i16> %x, <1 x i16>* %b) {
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%bb = load <1 x i16>, <1 x i16>* %b
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%tt = xor <1 x i16> %x, %bb
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store <1 x i16> %tt, <1 x i16>* %b
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br label %next
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next:
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ret <1 x i16> %tt
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}
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define <1 x i32> @test_1xi32(<1 x i32> %x, <1 x i32>* %b) {
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%bb = load <1 x i32>, <1 x i32>* %b
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%tt = xor <1 x i32> %x, %bb
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store <1 x i32> %tt, <1 x i32>* %b
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br label %next
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next:
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ret <1 x i32> %tt
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}
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define <1 x i64> @test_1xi64(<1 x i64> %x, <1 x i64>* %b) {
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%bb = load <1 x i64>, <1 x i64>* %b
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%tt = xor <1 x i64> %x, %bb
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store <1 x i64> %tt, <1 x i64>* %b
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br label %next
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next:
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ret <1 x i64> %tt
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}
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define <1 x i128> @test_1xi128(<1 x i128> %x, <1 x i128>* %b) {
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%bb = load <1 x i128>, <1 x i128>* %b
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%tt = xor <1 x i128> %x, %bb
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store <1 x i128> %tt, <1 x i128>* %b
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br label %next
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next:
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ret <1 x i128> %tt
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}
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define <1 x i256> @test_1xi256(<1 x i256> %x, <1 x i256>* %b) {
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%bb = load <1 x i256>, <1 x i256>* %b
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%tt = xor <1 x i256> %x, %bb
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store <1 x i256> %tt, <1 x i256>* %b
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br label %next
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next:
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ret <1 x i256> %tt
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}
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define <1 x i512> @test_1xi512(<1 x i512> %x, <1 x i512>* %b) {
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%bb = load <1 x i512>, <1 x i512>* %b
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%tt = xor <1 x i512> %x, %bb
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store <1 x i512> %tt, <1 x i512>* %b
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br label %next
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next:
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ret <1 x i512> %tt
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}
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define <2 x i8> @test_2xi8(<2 x i8> %x, <2 x i8>* %b) {
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%bb = load <2 x i8>, <2 x i8>* %b
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%tt = xor <2 x i8> %x, %bb
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store <2 x i8> %tt, <2 x i8>* %b
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br label %next
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next:
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ret <2 x i8> %tt
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}
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define <2 x i16> @test_2xi16(<2 x i16> %x, <2 x i16>* %b) {
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%bb = load <2 x i16>, <2 x i16>* %b
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%tt = xor <2 x i16> %x, %bb
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store <2 x i16> %tt, <2 x i16>* %b
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br label %next
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next:
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ret <2 x i16> %tt
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}
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define <2 x i32> @test_2xi32(<2 x i32> %x, <2 x i32>* %b) {
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%bb = load <2 x i32>, <2 x i32>* %b
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%tt = xor <2 x i32> %x, %bb
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store <2 x i32> %tt, <2 x i32>* %b
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br label %next
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next:
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ret <2 x i32> %tt
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}
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define <2 x i64> @test_2xi64(<2 x i64> %x, <2 x i64>* %b) {
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%bb = load <2 x i64>, <2 x i64>* %b
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%tt = xor <2 x i64> %x, %bb
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store <2 x i64> %tt, <2 x i64>* %b
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br label %next
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next:
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ret <2 x i64> %tt
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}
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define <2 x i128> @test_2xi128(<2 x i128> %x, <2 x i128>* %b) {
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%bb = load <2 x i128>, <2 x i128>* %b
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%tt = xor <2 x i128> %x, %bb
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store <2 x i128> %tt, <2 x i128>* %b
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br label %next
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next:
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ret <2 x i128> %tt
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}
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define <2 x i256> @test_2xi256(<2 x i256> %x, <2 x i256>* %b) {
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%bb = load <2 x i256>, <2 x i256>* %b
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%tt = xor <2 x i256> %x, %bb
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store <2 x i256> %tt, <2 x i256>* %b
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br label %next
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next:
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ret <2 x i256> %tt
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}
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define <2 x i512> @test_2xi512(<2 x i512> %x, <2 x i512>* %b) {
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%bb = load <2 x i512>, <2 x i512>* %b
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%tt = xor <2 x i512> %x, %bb
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store <2 x i512> %tt, <2 x i512>* %b
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br label %next
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next:
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ret <2 x i512> %tt
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}
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define <3 x i8> @test_3xi8(<3 x i8> %x, <3 x i8>* %b) {
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%bb = load <3 x i8>, <3 x i8>* %b
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%tt = xor <3 x i8> %x, %bb
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store <3 x i8> %tt, <3 x i8>* %b
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br label %next
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next:
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ret <3 x i8> %tt
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}
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define <3 x i16> @test_3xi16(<3 x i16> %x, <3 x i16>* %b) {
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%bb = load <3 x i16>, <3 x i16>* %b
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%tt = xor <3 x i16> %x, %bb
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store <3 x i16> %tt, <3 x i16>* %b
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br label %next
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next:
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ret <3 x i16> %tt
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}
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define <3 x i32> @test_3xi32(<3 x i32> %x, <3 x i32>* %b) {
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%bb = load <3 x i32>, <3 x i32>* %b
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%tt = xor <3 x i32> %x, %bb
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store <3 x i32> %tt, <3 x i32>* %b
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br label %next
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next:
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ret <3 x i32> %tt
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}
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define <3 x i64> @test_3xi64(<3 x i64> %x, <3 x i64>* %b) {
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%bb = load <3 x i64>, <3 x i64>* %b
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%tt = xor <3 x i64> %x, %bb
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store <3 x i64> %tt, <3 x i64>* %b
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br label %next
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next:
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ret <3 x i64> %tt
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}
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define <3 x i128> @test_3xi128(<3 x i128> %x, <3 x i128>* %b) {
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%bb = load <3 x i128>, <3 x i128>* %b
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%tt = xor <3 x i128> %x, %bb
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store <3 x i128> %tt, <3 x i128>* %b
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br label %next
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next:
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ret <3 x i128> %tt
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}
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define <3 x i256> @test_3xi256(<3 x i256> %x, <3 x i256>* %b) {
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%bb = load <3 x i256>, <3 x i256>* %b
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%tt = xor <3 x i256> %x, %bb
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store <3 x i256> %tt, <3 x i256>* %b
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br label %next
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next:
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ret <3 x i256> %tt
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}
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define <3 x i512> @test_3xi512(<3 x i512> %x, <3 x i512>* %b) {
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%bb = load <3 x i512>, <3 x i512>* %b
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%tt = xor <3 x i512> %x, %bb
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store <3 x i512> %tt, <3 x i512>* %b
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br label %next
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next:
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ret <3 x i512> %tt
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}
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define <4 x i8> @test_4xi8(<4 x i8> %x, <4 x i8>* %b) {
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%bb = load <4 x i8>, <4 x i8>* %b
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%tt = xor <4 x i8> %x, %bb
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store <4 x i8> %tt, <4 x i8>* %b
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br label %next
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next:
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ret <4 x i8> %tt
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}
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define <4 x i16> @test_4xi16(<4 x i16> %x, <4 x i16>* %b) {
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%bb = load <4 x i16>, <4 x i16>* %b
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%tt = xor <4 x i16> %x, %bb
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store <4 x i16> %tt, <4 x i16>* %b
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br label %next
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next:
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ret <4 x i16> %tt
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}
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define <4 x i32> @test_4xi32(<4 x i32> %x, <4 x i32>* %b) {
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%bb = load <4 x i32>, <4 x i32>* %b
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%tt = xor <4 x i32> %x, %bb
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store <4 x i32> %tt, <4 x i32>* %b
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br label %next
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next:
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ret <4 x i32> %tt
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}
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define <4 x i64> @test_4xi64(<4 x i64> %x, <4 x i64>* %b) {
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%bb = load <4 x i64>, <4 x i64>* %b
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%tt = xor <4 x i64> %x, %bb
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store <4 x i64> %tt, <4 x i64>* %b
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br label %next
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next:
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ret <4 x i64> %tt
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}
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define <4 x i128> @test_4xi128(<4 x i128> %x, <4 x i128>* %b) {
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%bb = load <4 x i128>, <4 x i128>* %b
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%tt = xor <4 x i128> %x, %bb
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store <4 x i128> %tt, <4 x i128>* %b
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br label %next
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next:
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ret <4 x i128> %tt
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}
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define <4 x i256> @test_4xi256(<4 x i256> %x, <4 x i256>* %b) {
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%bb = load <4 x i256>, <4 x i256>* %b
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%tt = xor <4 x i256> %x, %bb
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store <4 x i256> %tt, <4 x i256>* %b
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br label %next
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next:
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ret <4 x i256> %tt
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}
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define <4 x i512> @test_4xi512(<4 x i512> %x, <4 x i512>* %b) {
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%bb = load <4 x i512>, <4 x i512>* %b
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%tt = xor <4 x i512> %x, %bb
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store <4 x i512> %tt, <4 x i512>* %b
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br label %next
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next:
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ret <4 x i512> %tt
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}
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define <5 x i8> @test_5xi8(<5 x i8> %x, <5 x i8>* %b) {
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%bb = load <5 x i8>, <5 x i8>* %b
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%tt = xor <5 x i8> %x, %bb
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store <5 x i8> %tt, <5 x i8>* %b
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br label %next
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next:
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ret <5 x i8> %tt
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}
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define <5 x i16> @test_5xi16(<5 x i16> %x, <5 x i16>* %b) {
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%bb = load <5 x i16>, <5 x i16>* %b
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%tt = xor <5 x i16> %x, %bb
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store <5 x i16> %tt, <5 x i16>* %b
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br label %next
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next:
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ret <5 x i16> %tt
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}
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define <5 x i32> @test_5xi32(<5 x i32> %x, <5 x i32>* %b) {
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%bb = load <5 x i32>, <5 x i32>* %b
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%tt = xor <5 x i32> %x, %bb
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store <5 x i32> %tt, <5 x i32>* %b
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br label %next
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next:
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ret <5 x i32> %tt
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}
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define <5 x i64> @test_5xi64(<5 x i64> %x, <5 x i64>* %b) {
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%bb = load <5 x i64>, <5 x i64>* %b
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%tt = xor <5 x i64> %x, %bb
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store <5 x i64> %tt, <5 x i64>* %b
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br label %next
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next:
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ret <5 x i64> %tt
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}
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define <5 x i128> @test_5xi128(<5 x i128> %x, <5 x i128>* %b) {
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%bb = load <5 x i128>, <5 x i128>* %b
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%tt = xor <5 x i128> %x, %bb
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store <5 x i128> %tt, <5 x i128>* %b
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br label %next
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next:
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ret <5 x i128> %tt
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}
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define <5 x i256> @test_5xi256(<5 x i256> %x, <5 x i256>* %b) {
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%bb = load <5 x i256>, <5 x i256>* %b
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%tt = xor <5 x i256> %x, %bb
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store <5 x i256> %tt, <5 x i256>* %b
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br label %next
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next:
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ret <5 x i256> %tt
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}
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define <5 x i512> @test_5xi512(<5 x i512> %x, <5 x i512>* %b) {
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%bb = load <5 x i512>, <5 x i512>* %b
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%tt = xor <5 x i512> %x, %bb
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store <5 x i512> %tt, <5 x i512>* %b
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br label %next
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next:
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ret <5 x i512> %tt
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}
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