llvm-6502/test/CodeGen
James Molloy cd2647f4fd Don't create a MIN/MAX node if the underlying compare has more than one use.
If the compare in a select pattern has another use then it can't be removed, so we'd just
be creating repeated code if we created a min/max node.

Spotted by Matt Arsenault!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239037 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 13:48:23 +00:00
..
AArch64 Don't create a MIN/MAX node if the underlying compare has more than one use. 2015-06-04 13:48:23 +00:00
ARM ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
BPF
CPP
Generic
Hexagon [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized variable issue was fixed. Removing re-registering ASM backend. 2015-06-03 18:00:45 +00:00
Inputs
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR MIR Serialization: use correct line and column numbers for LLVM IR errors. 2015-05-29 17:05:41 +00:00
MSP430
NVPTX [NVPTXFavorNonGenericAddrSpaces] recursively trace into GEP and BitCast 2015-05-29 17:00:27 +00:00
PowerPC Add support for VSX FMA single-precision instructions to the PPC back end 2015-05-29 17:13:25 +00:00
R600 R600: Re-enable sub-reg liveness 2015-06-04 01:20:04 +00:00
SPARC
SystemZ
Thumb
Thumb2 ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
WinEH
X86 AVX-512: I brought back vector-shuffle-512-v8.ll test. 2015-06-04 07:49:56 +00:00
XCore