mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dabb41d93d
-- passing FP arguments to functions with more than 6 arguments -- passing FP arguments to varargs functions -- passing FP arguments to functions with no prototypes -- incorrect coloring for CC registers (both int and FP): interferences were being completely ignored for int CC and were considered but no spills were marked for fp CC! Also some code improvements: -- better interface to generating machine instr for common cases (many places still need to be updated to use this interface) -- annotations on MachineInstr to communicate information from one codegen phase to another (now used to pass information about CALL/JMPLCALL operands from selection to register allocation) -- all sizes and offests in class TargetData are uint64_t instead of uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2642 91177308-0d34-0410-b5e6-96231b3b80d8
1246 lines
41 KiB
C++
1246 lines
41 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// PhyRegAlloc.cpp
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//
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// Purpose:
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// Register allocation for LLVM.
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//
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// History:
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// 9/10/01 - Ruchira Sasanka - created.
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//**************************************************************************/
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrAnnot.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineFrameInfo.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/iOther.h"
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#include "llvm/CodeGen/RegAllocCommon.h"
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#include <iostream>
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#include <math.h>
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using std::cerr;
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// ***TODO: There are several places we add instructions. Validate the order
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// of adding these instructions.
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cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
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"enable register allocation debugging information",
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clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
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clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
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clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
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//----------------------------------------------------------------------------
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// RegisterAllocation pass front end...
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//----------------------------------------------------------------------------
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namespace {
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class RegisterAllocator : public FunctionPass {
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TargetMachine &Target;
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public:
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inline RegisterAllocator(TargetMachine &T) : Target(T) {}
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const char *getPassName() const { return "Register Allocation"; }
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bool runOnFunction(Function *F) {
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if (DEBUG_RA)
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cerr << "\n******************** Function "<< F->getName()
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<< " ********************\n";
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PhyRegAlloc PRA(F, Target, &getAnalysis<FunctionLiveVarInfo>(),
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&getAnalysis<LoopInfo>());
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PRA.allocateRegisters();
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if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
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return false;
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired(LoopInfo::ID);
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AU.addRequired(FunctionLiveVarInfo::ID);
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}
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};
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}
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Pass *getRegisterAllocator(TargetMachine &T) {
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return new RegisterAllocator(T);
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}
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
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FunctionLiveVarInfo *Lvi, LoopInfo *LDC)
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: TM(tm), Meth(F),
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mcInfo(MachineCodeForMethod::get(F)),
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LVI(Lvi), LRI(F, tm, RegClassList),
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MRI(tm.getRegInfo()),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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LoopDepthCalc(LDC) {
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// create each RegisterClass and put in RegClassList
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//
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for(unsigned int rc=0; rc < NumOfRegClasses; rc++)
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RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
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&ResColList));
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}
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//----------------------------------------------------------------------------
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// Destructor: Deletes register classes
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//----------------------------------------------------------------------------
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PhyRegAlloc::~PhyRegAlloc() {
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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delete RegClassList[rc];
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AddedInstrMap.clear();
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}
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs() {
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if (DEBUG_RA) cerr << "Creating LR lists ...\n";
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
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for (; HMI != HMIEnd ; ++HMI ) {
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if (HMI->first) {
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LiveRange *L = HMI->second; // get the LiveRange
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if (!L) {
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if( DEBUG_RA) {
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cerr << "\n*?!?Warning: Null liver range found for: "
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<< RAV(HMI->first) << "\n";
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}
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continue;
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}
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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RegClassList[ L->getRegClass()->getID() ];
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RC->addLRToIG(L); // add this LR to an IG
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}
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}
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}
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[rc]->createInterferenceGraph();
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if( DEBUG_RA)
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cerr << "LRLists Created!\n";
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}
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *Def,
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const ValueSet *LVSet,
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bool isCallInst) {
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ValueSet::const_iterator LIt = LVSet->begin();
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// get the live range of instruction
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//
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const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
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IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
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assert( IGNodeOfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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// for each live var in live variable set
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//
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for( ; LIt != LVSet->end(); ++LIt) {
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if (DEBUG_RA > 1)
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cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
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// get the live range corresponding to live var
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//
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LiveRange *LROfVar = LRI.getLiveRangeForValue(*LIt);
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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//
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if (LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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continue;
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// if 2 reg classes are the same set interference
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//
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if (RCOfDef == LROfVar->getRegClass()) {
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RCOfDef->setInterference( LROfDef, LROfVar);
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} else if (DEBUG_RA > 1) {
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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cerr << " warning: no live range for " << RAV(*LIt) << "\n";
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}
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}
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}
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}
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//----------------------------------------------------------------------------
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// For a call instruction, this method sets the CallInterference flag in
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// the LR of each variable live int the Live Variable Set live after the
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// call instruction (except the return value of the call instruction - since
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// the return value does not interfere with that call itself).
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//----------------------------------------------------------------------------
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void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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const ValueSet *LVSetAft) {
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if( DEBUG_RA)
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cerr << "\n For call inst: " << *MInst;
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ValueSet::const_iterator LIt = LVSetAft->begin();
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// for each live var in live variable set after machine inst
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//
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for( ; LIt != LVSetAft->end(); ++LIt) {
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// get the live range corresponding to live var
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//
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LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
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if( LR && DEBUG_RA) {
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cerr << "\n\tLR Aft Call: ";
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printSet(*LR);
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}
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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//
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if( LR ) {
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LR->setCallInterference();
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if( DEBUG_RA) {
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cerr << "\n ++Added call interf for LR: " ;
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printSet(*LR);
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}
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}
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}
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// Now find the LR of the return value of the call
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// We do this because, we look at the LV set *after* the instruction
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// to determine, which LRs must be saved across calls. The return value
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// of the call is live in this set - but it does not interfere with call
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// (i.e., we can allocate a volatile register to the return value)
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//
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CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
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if (const Value *RetVal = argDesc->getReturnValue()) {
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LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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RetValLR->clearCallInterference();
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}
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// If the CALL is an indirect call, find the LR of the function pointer.
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// That has a call interference because it conflicts with outgoing args.
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if( const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
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LiveRange *AddrValLR = LRI.getLiveRangeForValue( AddrVal );
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assert( AddrValLR && "No LR for indirect addr val of call");
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AddrValLR->setCallInterference();
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}
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass. Also, this method calculates the spill cost of each
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// Live Range (it is done in this method to save another pass over the code).
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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if(DEBUG_RA) cerr << "Creating interference graphs ...\n";
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unsigned BBLoopDepthCost;
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for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
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BBI != BBE; ++BBI) {
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// find the 10^(loop_depth) of this BB
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//
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BBLoopDepthCost = (unsigned) pow(10.0, LoopDepthCalc->getLoopDepth(*BBI));
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// get the iterator for machine instructions
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//
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator MII = MIVec.begin();
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// iterate over all the machine instructions in BB
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//
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for( ; MII != MIVec.end(); ++MII) {
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const MachineInstr *MInst = *MII;
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// get the LV set after the instruction
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//
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const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, *BBI);
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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if( isCallInst ) {
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// set the isCallInterference flag of each live range wich extends
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// accross this call instruction. This information is used by graph
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// coloring algo to avoid allocating volatile colors to live ranges
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// that span across calls (since they have to be saved/restored)
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//
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setCallInterferences(MInst, &LVSetAI);
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}
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// iterate over all MI operands to find defs
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//
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for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
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OpE = MInst->end(); OpI != OpE; ++OpI) {
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if (OpI.isDef()) // create a new LR iff this operand is a def
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addInterference(*OpI, &LVSetAI, isCallInst);
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// Calculate the spill cost of each live range
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//
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LiveRange *LR = LRI.getLiveRangeForValue(*OpI);
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if (LR) LR->addSpillCost(BBLoopDepthCost);
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}
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// if there are multiple defs in this instruction e.g. in SETX
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//
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if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
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addInterf4PseudoInstr(MInst);
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// Also add interference for any implicit definitions in a machine
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// instr (currently, only calls have this).
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//
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unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
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if( NumOfImpRefs > 0 ) {
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for(unsigned z=0; z < NumOfImpRefs; z++)
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if( MInst->implicitRefIsDefined(z) )
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addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
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}
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} // for all machine instructions in BB
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} // for all BBs in function
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// add interferences for function arguments. Since there are no explict
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// defs in the function for args, we have to add them manually
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//
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addInterferencesForArgs();
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if( DEBUG_RA)
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cerr << "Interference graphs calculted!\n";
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}
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//--------------------------------------------------------------------------
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// Pseudo instructions will be exapnded to multiple instructions by the
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// assembler. Consequently, all the opernds must get distinct registers.
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// Therefore, we mark all operands of a pseudo instruction as they interfere
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// with one another.
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//--------------------------------------------------------------------------
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void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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bool setInterf = false;
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// iterate over MI operands to find defs
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//
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for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
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ItE = MInst->end(); It1 != ItE; ++It1) {
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const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1);
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assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction");
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MachineInstr::const_val_op_iterator It2 = It1;
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for(++It2; It2 != ItE; ++It2) {
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const LiveRange *LROfOp2 = LRI.getLiveRangeForValue(*It2);
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if (LROfOp2) {
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RegClass *RCOfOp1 = LROfOp1->getRegClass();
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RegClass *RCOfOp2 = LROfOp2->getRegClass();
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if( RCOfOp1 == RCOfOp2 ){
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RCOfOp1->setInterference( LROfOp1, LROfOp2 );
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setInterf = true;
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}
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} // if Op2 has a LR
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} // for all other defs in machine instr
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} // for all operands in an instruction
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if (!setInterf && MInst->getNumOperands() > 2) {
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cerr << "\nInterf not set for any operand in pseudo instr:\n";
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cerr << *MInst;
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assert(0 && "Interf not set for pseudo instr with > 2 operands" );
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}
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}
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//----------------------------------------------------------------------------
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// This method will add interferences for incoming arguments to a function.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs() {
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// get the InSet of root BB
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const ValueSet &InSet = LVI->getInSetOfBB(Meth->front());
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// get the argument list
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const Function::ArgumentListType &ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Function::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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addInterference((Value*)*ArgIt, &InSet, false);// add interferences between
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// args and LVars at start
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if( DEBUG_RA > 1)
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cerr << " - %% adding interference for argument "
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<< RAV((const Value *)*ArgIt) << "\n";
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}
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}
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated reisters in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value. Also it calls target specific
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// methods to produce caller saving instructions. At the end, it adds all
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// additional instructions produced by the register allocator to the
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// instruction stream.
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//----------------------------------------------------------------------------
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//-----------------------------
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// Utility functions used below
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//-----------------------------
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inline void
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PrependInstructions(vector<MachineInstr *> &IBef,
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MachineCodeForBasicBlock& MIVec,
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MachineCodeForBasicBlock::iterator& MII,
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const std::string& msg)
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{
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if (!IBef.empty())
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{
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MachineInstr* OrigMI = *MII;
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std::vector<MachineInstr *>::iterator AdIt;
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for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
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{
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if (DEBUG_RA) {
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if (OrigMI) cerr << "For MInst: " << *OrigMI;
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cerr << msg << " PREPENDed instr: " << **AdIt << "\n";
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}
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MII = MIVec.insert(MII, *AdIt);
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++MII;
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}
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}
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}
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inline void
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AppendInstructions(std::vector<MachineInstr *> &IAft,
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MachineCodeForBasicBlock& MIVec,
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MachineCodeForBasicBlock::iterator& MII,
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const std::string& msg)
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{
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if (!IAft.empty())
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{
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MachineInstr* OrigMI = *MII;
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std::vector<MachineInstr *>::iterator AdIt;
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for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
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{
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if(DEBUG_RA) {
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if (OrigMI) cerr << "For MInst: " << *OrigMI;
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cerr << msg << " APPENDed instr: " << **AdIt << "\n";
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}
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++MII; // insert before the next instruction
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MII = MIVec.insert(MII, *AdIt);
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}
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}
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}
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void PhyRegAlloc::updateMachineCode()
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{
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const BasicBlock* entryBB = Meth->getEntryNode();
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if (entryBB) {
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MachineCodeForBasicBlock& MIVec = entryBB->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MII = MIVec.begin();
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// Insert any instructions needed at method entry
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PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MIVec, MII,
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"At function entry: \n");
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assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
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"InstrsAfter should be unnecessary since we are just inserting at "
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"the function entry point here.");
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}
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for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
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BBI != BBE; ++BBI) {
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// iterate over all the machine instructions in BB
|
|
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
|
for(MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
|
MII != MIVec.end(); ++MII) {
|
|
|
|
MachineInstr *MInst = *MII;
|
|
|
|
unsigned Opcode = MInst->getOpCode();
|
|
|
|
// do not process Phis
|
|
if (TM.getInstrInfo().isDummyPhiInstr(Opcode))
|
|
continue;
|
|
|
|
// Now insert speical instructions (if necessary) for call/return
|
|
// instructions.
|
|
//
|
|
if (TM.getInstrInfo().isCall(Opcode) ||
|
|
TM.getInstrInfo().isReturn(Opcode)) {
|
|
|
|
AddedInstrns &AI = AddedInstrMap[MInst];
|
|
|
|
// Tmp stack poistions are needed by some calls that have spilled args
|
|
// So reset it before we call each such method
|
|
//
|
|
mcInfo.popAllTempValues(TM);
|
|
|
|
if (TM.getInstrInfo().isCall(Opcode))
|
|
MRI.colorCallArgs(MInst, LRI, &AI, *this, *BBI);
|
|
else if (TM.getInstrInfo().isReturn(Opcode))
|
|
MRI.colorRetValue(MInst, LRI, &AI);
|
|
}
|
|
|
|
|
|
/* -- Using above code instead of this
|
|
|
|
// if this machine instr is call, insert caller saving code
|
|
|
|
if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
|
|
MRI.insertCallerSavingCode(MInst, *BBI, *this );
|
|
|
|
*/
|
|
|
|
|
|
// reset the stack offset for temporary variables since we may
|
|
// need that to spill
|
|
// mcInfo.popAllTempValues(TM);
|
|
// TODO ** : do later
|
|
|
|
//for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
|
|
|
|
|
|
// Now replace set the registers for operands in the machine instruction
|
|
//
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister) {
|
|
|
|
const Value *const Val = Op.getVRegValue();
|
|
|
|
// delete this condition checking later (must assert if Val is null)
|
|
if( !Val) {
|
|
if (DEBUG_RA)
|
|
cerr << "Warning: NULL Value found for operand\n";
|
|
continue;
|
|
}
|
|
assert( Val && "Value is NULL");
|
|
|
|
LiveRange *const LR = LRI.getLiveRangeForValue(Val);
|
|
|
|
if ( !LR ) {
|
|
|
|
// nothing to worry if it's a const or a label
|
|
|
|
if (DEBUG_RA) {
|
|
cerr << "*NO LR for operand : " << Op ;
|
|
cerr << " [reg:" << Op.getAllocatedRegNum() << "]";
|
|
cerr << " in inst:\t" << *MInst << "\n";
|
|
}
|
|
|
|
// if register is not allocated, mark register as invalid
|
|
if( Op.getAllocatedRegNum() == -1)
|
|
Op.setRegForValue( MRI.getInvalidRegNum());
|
|
|
|
|
|
continue;
|
|
}
|
|
|
|
unsigned RCID = (LR->getRegClass())->getID();
|
|
|
|
if( LR->hasColor() ) {
|
|
Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
|
|
}
|
|
else {
|
|
|
|
// LR did NOT receive a color (register). Now, insert spill code
|
|
// for spilled opeands in this machine instruction
|
|
|
|
//assert(0 && "LR must be spilled");
|
|
insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
|
|
|
|
}
|
|
}
|
|
|
|
} // for each operand
|
|
|
|
|
|
// Now add instructions that the register allocator inserts before/after
|
|
// this machine instructions (done only for calls/rets/incoming args)
|
|
// We do this here, to ensure that spill for an instruction is inserted
|
|
// closest as possible to an instruction (see above insertCode4Spill...)
|
|
//
|
|
// If there are instructions to be added, *before* this machine
|
|
// instruction, add them now.
|
|
//
|
|
if(AddedInstrMap.count(MInst)) {
|
|
PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MIVec, MII,"");
|
|
}
|
|
|
|
// If there are instructions to be added *after* this machine
|
|
// instruction, add them now
|
|
//
|
|
if (!AddedInstrMap[MInst].InstrnsAfter.empty()) {
|
|
|
|
// if there are delay slots for this instruction, the instructions
|
|
// added after it must really go after the delayed instruction(s)
|
|
// So, we move the InstrAfter of the current instruction to the
|
|
// corresponding delayed instruction
|
|
|
|
unsigned delay;
|
|
if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
|
|
move2DelayedInstr(MInst, *(MII+delay) );
|
|
|
|
if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
|
|
}
|
|
|
|
else {
|
|
// Here we can add the "instructions after" to the current
|
|
// instruction since there are no delay slots for this instruction
|
|
AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MIVec, MII,"");
|
|
} // if not delay
|
|
|
|
}
|
|
|
|
} // for each machine instruction
|
|
}
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method inserts spill code for AN operand whose LR was spilled.
|
|
// This method may be called several times for a single machine instruction
|
|
// if it contains many spilled operands. Each time it is called, it finds
|
|
// a register which is not live at that instruction and also which is not
|
|
// used by other spilled operands of the same instruction. Then it uses
|
|
// this register temporarily to accomodate the spilled value.
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
|
MachineInstr *MInst,
|
|
const BasicBlock *BB,
|
|
const unsigned OpNum) {
|
|
|
|
assert(! TM.getInstrInfo().isCall(MInst->getOpCode()) &&
|
|
(! TM.getInstrInfo().isReturn(MInst->getOpCode())) &&
|
|
"Arg of a call/ret must be handled elsewhere");
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
bool isDef = MInst->operandIsDefined(OpNum);
|
|
unsigned RegType = MRI.getRegType( LR );
|
|
int SpillOff = LR->getSpillOffFromFP();
|
|
RegClass *RC = LR->getRegClass();
|
|
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
|
|
|
|
mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
|
|
|
|
MachineInstr *MIBef=NULL, *MIAft=NULL;
|
|
vector<MachineInstr*> AdIMid;
|
|
|
|
int TmpRegU = getUsableUniRegAtMI(RC, RegType, MInst,&LVSetBef, MIBef, MIAft);
|
|
|
|
// get the added instructions for this instruciton
|
|
AddedInstrns &AI = AddedInstrMap[MInst];
|
|
|
|
if (!isDef) {
|
|
// for a USE, we have to load the value of LR from stack to a TmpReg
|
|
// and use the TmpReg as one operand of instruction
|
|
|
|
// actual loading instruction
|
|
MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType, AdIMid);
|
|
AI.InstrnsBefore.insert(AI.InstrnsBefore.end(),
|
|
AdIMid.begin(), AdIMid.end());
|
|
|
|
if(MIBef)
|
|
AI.InstrnsBefore.push_back(MIBef);
|
|
|
|
if(MIAft)
|
|
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft);
|
|
|
|
} else { // if this is a Def
|
|
// for a DEF, we have to store the value produced by this instruction
|
|
// on the stack position allocated for this LR
|
|
|
|
// actual storing instruction
|
|
MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType, AdIMid);
|
|
|
|
if (MIBef)
|
|
AI.InstrnsBefore.push_back(MIBef);
|
|
|
|
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(),
|
|
AdIMid.begin(), AdIMid.end());
|
|
|
|
if (MIAft)
|
|
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft);
|
|
|
|
} // if !DEF
|
|
|
|
cerr << "\nFor Inst " << *MInst;
|
|
cerr << " - SPILLED LR: "; printSet(*LR);
|
|
cerr << "\n - Added Instructions:";
|
|
if (MIBef) cerr << *MIBef;
|
|
for (vector<MachineInstr*>::const_iterator II=AdIMid.begin();
|
|
II != AdIMid.end(); ++II)
|
|
cerr << **II;
|
|
if (MIAft) cerr << *MIAft;
|
|
|
|
Op.setRegForValue(TmpRegU); // set the opearnd
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// We can use the following method to get a temporary register to be used
|
|
// BEFORE any given machine instruction. If there is a register available,
|
|
// this method will simply return that register and set MIBef = MIAft = NULL.
|
|
// Otherwise, it will return a register and MIAft and MIBef will contain
|
|
// two instructions used to free up this returned register.
|
|
// Returned register number is the UNIFIED register number
|
|
//----------------------------------------------------------------------------
|
|
|
|
int PhyRegAlloc::getUsableUniRegAtMI(RegClass *RC,
|
|
const int RegType,
|
|
const MachineInstr *MInst,
|
|
const ValueSet *LVSetBef,
|
|
MachineInstr *&MIBef,
|
|
MachineInstr *&MIAft) {
|
|
|
|
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
|
|
|
|
|
|
if( RegU != -1) {
|
|
// we found an unused register, so we can simply use it
|
|
MIBef = MIAft = NULL;
|
|
}
|
|
else {
|
|
// we couldn't find an unused register. Generate code to free up a reg by
|
|
// saving it on stack and restoring after the instruction
|
|
|
|
int TmpOff = mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
|
|
|
|
RegU = getUniRegNotUsedByThisInst(RC, MInst);
|
|
|
|
vector<MachineInstr*> mvec;
|
|
|
|
MRI.cpReg2MemMI(RegU, MRI.getFramePointer(), TmpOff, RegType, mvec);
|
|
assert(mvec.size() == 1 && "Need to return a vector here too");
|
|
MIBef = * mvec.begin();
|
|
|
|
MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, RegU, RegType, mvec);
|
|
assert(mvec.size() == 1 && "Need to return a vector here too");
|
|
MIAft = * mvec.begin();
|
|
}
|
|
|
|
return RegU;
|
|
}
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method is called to get a new unused register that can be used to
|
|
// accomodate a spilled value.
|
|
// This method may be called several times for a single machine instruction
|
|
// if it contains many spilled operands. Each time it is called, it finds
|
|
// a register which is not live at that instruction and also which is not
|
|
// used by other spilled operands of the same instruction.
|
|
// Return register number is relative to the register class. NOT
|
|
// unified number
|
|
//----------------------------------------------------------------------------
|
|
int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
|
|
const MachineInstr *MInst,
|
|
const ValueSet *LVSetBef) {
|
|
|
|
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
for(unsigned i=0; i < NumAvailRegs; i++) // Reset array
|
|
IsColorUsedArr[i] = false;
|
|
|
|
ValueSet::const_iterator LIt = LVSetBef->begin();
|
|
|
|
// for each live var in live variable set after machine inst
|
|
for( ; LIt != LVSetBef->end(); ++LIt) {
|
|
|
|
// get the live range corresponding to live var
|
|
LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
|
|
|
|
// LR can be null if it is a const since a const
|
|
// doesn't have a dominating def - see Assumptions above
|
|
if( LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor() )
|
|
IsColorUsedArr[ LRofLV->getColor() ] = true;
|
|
}
|
|
|
|
// It is possible that one operand of this MInst was already spilled
|
|
// and it received some register temporarily. If that's the case,
|
|
// it is recorded in machine operand. We must skip such registers.
|
|
|
|
setRelRegsUsedByThisInst(RC, MInst);
|
|
|
|
unsigned c; // find first unused color
|
|
for( c=0; c < NumAvailRegs; c++)
|
|
if( ! IsColorUsedArr[ c ] ) break;
|
|
|
|
if(c < NumAvailRegs)
|
|
return MRI.getUnifiedRegNum(RC->getID(), c);
|
|
else
|
|
return -1;
|
|
|
|
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// Get any other register in a register class, other than what is used
|
|
// by operands of a machine instruction. Returns the unified reg number.
|
|
//----------------------------------------------------------------------------
|
|
int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
|
const MachineInstr *MInst) {
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
|
|
|
|
|
for(unsigned i=0; i < NumAvailRegs ; i++) // Reset array
|
|
IsColorUsedArr[i] = false;
|
|
|
|
setRelRegsUsedByThisInst(RC, MInst);
|
|
|
|
unsigned c; // find first unused color
|
|
for( c=0; c < RC->getNumOfAvailRegs(); c++)
|
|
if( ! IsColorUsedArr[ c ] ) break;
|
|
|
|
if(c < NumAvailRegs)
|
|
return MRI.getUnifiedRegNum(RC->getID(), c);
|
|
else
|
|
assert( 0 && "FATAL: No free register could be found in reg class!!");
|
|
return 0;
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method modifies the IsColorUsedArr of the register class passed to it.
|
|
// It sets the bits corresponding to the registers used by this machine
|
|
// instructions. Both explicit and implicit operands are set.
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
|
|
const MachineInstr *MInst ) {
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
const MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister ) {
|
|
|
|
const Value *const Val = Op.getVRegValue();
|
|
|
|
if( Val )
|
|
if( MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
|
|
int Reg;
|
|
if( (Reg=Op.getAllocatedRegNum()) != -1) {
|
|
IsColorUsedArr[ Reg ] = true;
|
|
}
|
|
else {
|
|
// it is possilbe that this operand still is not marked with
|
|
// a register but it has a LR and that received a color
|
|
|
|
LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
|
if( LROfVal)
|
|
if( LROfVal->hasColor() )
|
|
IsColorUsedArr[ LROfVal->getColor() ] = true;
|
|
}
|
|
|
|
} // if reg classes are the same
|
|
}
|
|
else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
|
IsColorUsedArr[ Op.getMachineRegNum() ] = true;
|
|
}
|
|
}
|
|
|
|
// If there are implicit references, mark them as well
|
|
|
|
for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
|
|
|
|
LiveRange *const LRofImpRef =
|
|
LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
|
|
|
|
if(LRofImpRef && LRofImpRef->hasColor())
|
|
IsColorUsedArr[LRofImpRef->getColor()] = true;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// If there are delay slots for an instruction, the instructions
|
|
// added after it must really go after the delayed instruction(s).
|
|
// So, we move the InstrAfter of that instruction to the
|
|
// corresponding delayed instruction using the following method.
|
|
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
|
|
const MachineInstr *DelayedMI) {
|
|
|
|
// "added after" instructions of the original instr
|
|
std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
|
|
|
|
// "added instructions" of the delayed instr
|
|
AddedInstrns &DelayAdI = AddedInstrMap[DelayedMI];
|
|
|
|
// "added after" instructions of the delayed instr
|
|
std::vector<MachineInstr *> &DelayedAft = DelayAdI.InstrnsAfter;
|
|
|
|
// go thru all the "added after instructions" of the original instruction
|
|
// and append them to the "addded after instructions" of the delayed
|
|
// instructions
|
|
DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
|
|
|
|
// empty the "added after instructions" of the original instruction
|
|
OrigAft.clear();
|
|
}
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method prints the code with registers after register allocation is
|
|
// complete.
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::printMachineCode()
|
|
{
|
|
|
|
cerr << "\n;************** Function " << Meth->getName()
|
|
<< " *****************\n";
|
|
|
|
for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
|
|
BBI != BBE; ++BBI) {
|
|
cerr << "\n"; printLabel(*BBI); cerr << ": ";
|
|
|
|
// get the iterator for machine instructions
|
|
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
|
MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
|
|
|
// iterate over all the machine instructions in BB
|
|
for( ; MII != MIVec.end(); ++MII) {
|
|
MachineInstr *const MInst = *MII;
|
|
|
|
cerr << "\n\t";
|
|
cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister /*||
|
|
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
|
|
|
|
const Value *const Val = Op.getVRegValue () ;
|
|
// ****this code is temporary till NULL Values are fixed
|
|
if( ! Val ) {
|
|
cerr << "\t<*NULL*>";
|
|
continue;
|
|
}
|
|
|
|
// if a label or a constant
|
|
if(isa<BasicBlock>(Val)) {
|
|
cerr << "\t"; printLabel( Op.getVRegValue () );
|
|
} else {
|
|
// else it must be a register value
|
|
const int RegNum = Op.getAllocatedRegNum();
|
|
|
|
cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
|
|
if (Val->hasName() )
|
|
cerr << "(" << Val->getName() << ")";
|
|
else
|
|
cerr << "(" << Val << ")";
|
|
|
|
if( Op.opIsDef() )
|
|
cerr << "*";
|
|
|
|
const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
|
if( LROfVal )
|
|
if( LROfVal->hasSpillOffset() )
|
|
cerr << "$";
|
|
}
|
|
|
|
}
|
|
else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
|
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
|
|
}
|
|
|
|
else
|
|
cerr << "\t" << Op; // use dump field
|
|
}
|
|
|
|
|
|
|
|
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
|
|
if( NumOfImpRefs > 0) {
|
|
cerr << "\tImplicit:";
|
|
|
|
for(unsigned z=0; z < NumOfImpRefs; z++)
|
|
cerr << RAV(MInst->getImplicitRef(z)) << "\t";
|
|
}
|
|
|
|
} // for all machine instructions
|
|
|
|
cerr << "\n";
|
|
|
|
} // for all BBs
|
|
|
|
cerr << "\n";
|
|
}
|
|
|
|
|
|
#if 0
|
|
|
|
//----------------------------------------------------------------------------
|
|
//
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::colorCallRetArgs()
|
|
{
|
|
|
|
CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
|
|
CallRetInstrListType::const_iterator It = CallRetInstList.begin();
|
|
|
|
for( ; It != CallRetInstList.end(); ++It ) {
|
|
|
|
const MachineInstr *const CRMI = *It;
|
|
unsigned OpCode = CRMI->getOpCode();
|
|
|
|
// get the added instructions for this Call/Ret instruciton
|
|
AddedInstrns &AI = AddedInstrMap[CRMI];
|
|
|
|
// Tmp stack positions are needed by some calls that have spilled args
|
|
// So reset it before we call each such method
|
|
//mcInfo.popAllTempValues(TM);
|
|
|
|
|
|
if (TM.getInstrInfo().isCall(OpCode))
|
|
MRI.colorCallArgs(CRMI, LRI, &AI, *this);
|
|
else if (TM.getInstrInfo().isReturn(OpCode))
|
|
MRI.colorRetValue(CRMI, LRI, &AI);
|
|
else
|
|
assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::colorIncomingArgs()
|
|
{
|
|
const BasicBlock *const FirstBB = Meth->front();
|
|
const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
|
|
assert(FirstMI && "No machine instruction in entry BB");
|
|
|
|
MRI.colorMethodArgs(Meth, LRI, &AddedInstrAtEntry);
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// Used to generate a label for a basic block
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::printLabel(const Value *const Val) {
|
|
if (Val->hasName())
|
|
cerr << Val->getName();
|
|
else
|
|
cerr << "Label" << Val;
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method calls setSugColorUsable method of each live range. This
|
|
// will determine whether the suggested color of LR is really usable.
|
|
// A suggested color is not usable when the suggested color is volatile
|
|
// AND when there are call interferences
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::markUnusableSugColors()
|
|
{
|
|
if(DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n";
|
|
|
|
// hash map iterator
|
|
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
|
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
|
|
|
for(; HMI != HMIEnd ; ++HMI ) {
|
|
if (HMI->first) {
|
|
LiveRange *L = HMI->second; // get the LiveRange
|
|
if (L) {
|
|
if(L->hasSuggestedColor()) {
|
|
int RCID = L->getRegClass()->getID();
|
|
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
|
L->isCallInterference() )
|
|
L->setSuggestedColorUsable( false );
|
|
else
|
|
L->setSuggestedColorUsable( true );
|
|
}
|
|
} // if L->hasSuggestedColor()
|
|
}
|
|
} // for all LR's in hash map
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// The following method will set the stack offsets of the live ranges that
|
|
// are decided to be spillled. This must be called just after coloring the
|
|
// LRs using the graph coloring algo. For each live range that is spilled,
|
|
// this method allocate a new spill position on the stack.
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
|
|
if (DEBUG_RA) cerr << "\nsetting LR stack offsets ...\n";
|
|
|
|
LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
|
|
LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
|
|
|
|
for( ; HMI != HMIEnd ; ++HMI) {
|
|
if (HMI->first && HMI->second) {
|
|
LiveRange *L = HMI->second; // get the LiveRange
|
|
if (!L->hasColor()) // NOTE: ** allocating the size of long Type **
|
|
L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy));
|
|
}
|
|
} // for all LR's in hash map
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// The entry pont to Register Allocation
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::allocateRegisters()
|
|
{
|
|
|
|
// make sure that we put all register classes into the RegClassList
|
|
// before we call constructLiveRanges (now done in the constructor of
|
|
// PhyRegAlloc class).
|
|
//
|
|
LRI.constructLiveRanges(); // create LR info
|
|
|
|
if (DEBUG_RA)
|
|
LRI.printLiveRanges();
|
|
|
|
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
|
|
|
buildInterferenceGraphs(); // build IGs in all reg classes
|
|
|
|
|
|
if (DEBUG_RA) {
|
|
// print all LRs in all reg classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIG();
|
|
}
|
|
|
|
|
|
LRI.coalesceLRs(); // coalesce all live ranges
|
|
|
|
|
|
if( DEBUG_RA) {
|
|
// print all LRs in all reg classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIG();
|
|
}
|
|
|
|
|
|
// mark un-usable suggested color before graph coloring algorithm.
|
|
// When this is done, the graph coloring algo will not reserve
|
|
// suggested color unnecessarily - they can be used by another LR
|
|
//
|
|
markUnusableSugColors();
|
|
|
|
// color all register classes using the graph coloring algo
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->colorAllRegs();
|
|
|
|
// Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
|
|
// a poistion for such spilled LRs
|
|
//
|
|
allocateStackSpace4SpilledLRs();
|
|
|
|
mcInfo.popAllTempValues(TM); // TODO **Check
|
|
|
|
// color incoming args - if the correct color was not received
|
|
// insert code to copy to the correct register
|
|
//
|
|
colorIncomingArgs();
|
|
|
|
// Now update the machine code with register names and add any
|
|
// additional code inserted by the register allocator to the instruction
|
|
// stream
|
|
//
|
|
updateMachineCode();
|
|
|
|
if (DEBUG_RA) {
|
|
MachineCodeForMethod::get(Meth).dump();
|
|
printMachineCode(); // only for DEBUGGING
|
|
}
|
|
}
|
|
|
|
|
|
|