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225ca9cdd7
important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
3.3 KiB
C++
90 lines
3.3 KiB
C++
//===- MipsCallingConv.td - Calling Conventions for Mips --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for Mips architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>:
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CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Mips O32 Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsO32 : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The first 4 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3]>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32], CCAssignToStack<4, 4>>
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]>;
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def RetCC_MipsO32 : CallingConv<[
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// i32 are returned in registers V0, V1
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CCIfType<[i32], CCAssignToReg<[V0, V1]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips EABI Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsEABI : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
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// Single fp arguments are passed in pairs within 32-bit mode
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CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
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CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
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CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
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CCAssignToReg<[F12, F14, F16, F18]>>>,
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// The first 4 doubl fp arguments are passed in single fp registers.
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
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CCAssignToReg<[D6, D7, D8, D9]>>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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// Integer values get stored in stack slots that are 8 bytes in
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// size and 8-byte aligned.
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>>
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]>;
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def RetCC_MipsEABI : CallingConv<[
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// i32 are returned in registers V0, V1
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CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
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// f32 are returned in registers F0, F1
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CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
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// f64 are returned in register D0
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips Calling Convention Dispatch
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//===----------------------------------------------------------------------===//
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def CC_Mips : CallingConv<[
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CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
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CCDelegateTo<CC_MipsO32>
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]>;
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def RetCC_Mips : CallingConv<[
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CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
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CCDelegateTo<RetCC_MipsO32>
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]>;
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