Dan Gohman 525178cdbf Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to ...

use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8

2007-10-08 18:33:35 +00:00

..

CallingConvLower.cpp

propagate struct size and alignment of byval arguments to the DAG

2007-08-10 14:44:42 +00:00

DAGCombiner.cpp

DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI.

2007-10-08 17:57:15 +00:00

LegalizeDAG.cpp

Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to

2007-10-08 18:33:35 +00:00

Makefile

For PR780:

2006-07-26 16:18:00 +00:00

ScheduleDAG.cpp

If a node that defines a physical register that is expensive to copy. The

2007-10-05 01:39:18 +00:00

ScheduleDAGList.cpp

Trim some unneeded fields.

2007-09-28 19:24:24 +00:00

ScheduleDAGRRList.cpp

Fix a typo in a comment.

2007-10-05 14:11:58 +00:00

SelectionDAG.cpp

Add convenience overloads of SelectionDAG::getNode that take a SDVTList

2007-10-08 15:49:58 +00:00

SelectionDAGISel.cpp

In -debug mode, dump SelectionDAGs both before and after the

2007-10-08 15:12:17 +00:00

SelectionDAGPrinter.cpp

Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered.

2007-09-25 01:54:36 +00:00

TargetLowering.cpp

Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to

2007-10-08 18:33:35 +00:00