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These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8
629 lines
22 KiB
C++
629 lines
22 KiB
C++
//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PPCRegisterInfo.h"
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#include "PPC.h"
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#include "PPCFrameLowering.h"
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#include "PPCInstrBuilder.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include <cstdlib>
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#define GET_REGINFO_TARGET_DESC
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#include "PPCGenRegisterInfo.inc"
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using namespace llvm;
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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const TargetInstrInfo &tii)
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: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
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ST.isPPC64() ? 0 : 1,
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ST.isPPC64() ? 0 : 1),
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Subtarget(ST), TII(tii) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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// 64-bit
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ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
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ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
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ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
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ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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if (Kind == 1) {
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if (Subtarget.isPPC64())
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return &PPC::G8RC_NOX0RegClass;
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return &PPC::GPRC_NOR0RegClass;
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}
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if (Subtarget.isPPC64())
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return &PPC::G8RCRegClass;
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return &PPC::GPRCRegClass;
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}
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const uint16_t*
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PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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if (Subtarget.isDarwinABI())
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return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
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CSR_Darwin32_SaveList;
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return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
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}
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const uint32_t*
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PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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if (Subtarget.isDarwinABI())
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return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
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CSR_Darwin32_RegMask;
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return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
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}
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const uint32_t*
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PPCRegisterInfo::getNoPreservedMask() const {
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// The naming here is inverted: The CSR_NoRegs_Altivec has the
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// Altivec registers masked so that they're not saved and restored around
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// instructions with this preserved mask.
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if (!Subtarget.hasAltivec())
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return CSR_NoRegs_Altivec_RegMask;
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return CSR_NoRegs_RegMask;
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}
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BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const PPCFrameLowering *PPCFI =
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static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
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// The ZERO register is not really a register, but the representation of r0
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// when used in instructions that treat r0 as the constant 0.
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Reserved.set(PPC::ZERO);
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Reserved.set(PPC::ZERO8);
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// The FP register is also not really a register, but is the representation
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// of the frame pointer register used by ISD::FRAMEADDR.
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Reserved.set(PPC::FP);
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Reserved.set(PPC::FP8);
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Reserved.set(PPC::R0);
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Reserved.set(PPC::R1);
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Reserved.set(PPC::LR);
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Reserved.set(PPC::LR8);
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Reserved.set(PPC::RM);
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// The SVR4 ABI reserves r2 and r13
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if (Subtarget.isSVR4ABI()) {
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Reserved.set(PPC::R2); // System-reserved register
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Reserved.set(PPC::R13); // Small Data Area pointer register
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}
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// On PPC64, r13 is the thread pointer. Never allocate this register.
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if (Subtarget.isPPC64()) {
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Reserved.set(PPC::R13);
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Reserved.set(PPC::X0);
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Reserved.set(PPC::X1);
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Reserved.set(PPC::X13);
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if (PPCFI->needsFP(MF))
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Reserved.set(PPC::X31);
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// The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
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if (Subtarget.isSVR4ABI()) {
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Reserved.set(PPC::X2);
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}
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}
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if (PPCFI->needsFP(MF))
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Reserved.set(PPC::R31);
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return Reserved;
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}
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unsigned
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PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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const unsigned DefaultSafety = 1;
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switch (RC->getID()) {
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default:
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return 0;
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case PPC::G8RC_NOX0RegClassID:
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case PPC::GPRC_NOR0RegClassID:
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case PPC::G8RCRegClassID:
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case PPC::GPRCRegClassID: {
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unsigned FP = TFI->hasFP(MF) ? 1 : 0;
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return 32 - FP - DefaultSafety;
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}
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case PPC::F8RCRegClassID:
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case PPC::F4RCRegClassID:
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case PPC::VRRCRegClassID:
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return 32 - DefaultSafety;
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case PPC::CRRCRegClassID:
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return 8 - DefaultSafety;
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}
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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/// lowerDynamicAlloc - Generate the code for allocating an object in the
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/// current frame. The sequence of code with be in the general form
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///
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/// addi R0, SP, \#frameSize ; get the address of the previous frame
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/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
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/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
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///
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void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
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// Get the instruction.
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MachineInstr &MI = *II;
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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// Get the basic block's function.
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MachineFunction &MF = *MBB.getParent();
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Determine whether 64-bit pointers are used.
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bool LP64 = Subtarget.isPPC64();
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DebugLoc dl = MI.getDebugLoc();
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// Get the maximum call stack size.
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unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
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// Get the total frame size.
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unsigned FrameSize = MFI->getStackSize();
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// Get stack alignments.
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unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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if (MaxAlign > TargetAlign)
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report_fatal_error("Dynamic alloca with large aligns not supported");
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// Determine the previous frame's address. If FrameSize can't be
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// represented as 16 bits or we need special alignment, then we load the
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// previous frame's address from 0(SP). Why not do an addis of the hi?
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// Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
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// Constructing the constant and adding would take 3 instructions.
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// Fortunately, a frame greater than 32K is rare.
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
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.addReg(PPC::R31)
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.addImm(FrameSize);
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} else if (LP64) {
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BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
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.addImm(0)
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.addReg(PPC::X1);
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} else {
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BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
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.addImm(0)
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.addReg(PPC::R1);
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}
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// Grow the stack and update the stack pointer link, then determine the
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// address of new allocated space.
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if (LP64) {
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
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.addReg(Reg, RegState::Kill)
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.addReg(PPC::X1)
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.addReg(MI.getOperand(1).getReg());
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if (!MI.getOperand(1).isKill())
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
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.addReg(PPC::X1)
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.addImm(maxCallFrameSize);
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else
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// Implicitly kill the register.
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
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.addReg(PPC::X1)
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.addImm(maxCallFrameSize)
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.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
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} else {
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BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
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.addReg(Reg, RegState::Kill)
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.addReg(PPC::R1)
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.addReg(MI.getOperand(1).getReg());
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if (!MI.getOperand(1).isKill())
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
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.addReg(PPC::R1)
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.addImm(maxCallFrameSize);
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else
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// Implicitly kill the register.
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
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.addReg(PPC::R1)
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.addImm(maxCallFrameSize)
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.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
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}
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// Discard the DYNALLOC instruction.
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MBB.erase(II);
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}
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/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
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/// reserving a whole register (R0), we scrounge for one here. This generates
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/// code like this:
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///
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/// mfcr rA ; Move the conditional register into GPR rA.
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/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
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/// stw rA, FI ; Store rA to the frame.
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///
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void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const {
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// Get the instruction.
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MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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bool LP64 = Subtarget.isPPC64();
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unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
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unsigned SrcReg = MI.getOperand(0).getReg();
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// We need to store the CR in the low 4-bits of the saved value. First, issue
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// an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
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.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
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// If the saved register wasn't CR0, shift the bits left so that they are in
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// CR0's slot.
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if (SrcReg != PPC::CR0)
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// rlwinm rA, rA, ShiftBits, 0, 31.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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.addReg(Reg, RegState::Kill)
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.addImm(getPPCRegisterNumbering(SrcReg) * 4)
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.addImm(0)
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.addImm(31);
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addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
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.addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
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FrameIndex);
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// Discard the pseudo instruction.
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MBB.erase(II);
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}
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void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const {
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// Get the instruction.
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MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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bool LP64 = Subtarget.isPPC64();
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unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
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unsigned DestReg = MI.getOperand(0).getReg();
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assert(MI.definesRegister(DestReg) &&
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"RESTORE_CR does not define its destination");
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addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
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Reg), FrameIndex);
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// If the reloaded register isn't CR0, shift the bits right so that they are
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// in the right CR's slot.
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if (DestReg != PPC::CR0) {
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unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
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// rlwinm r11, r11, 32-ShiftBits, 0, 31.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
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.addReg(Reg).addImm(32-ShiftBits).addImm(0)
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.addImm(31);
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}
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
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.addReg(Reg);
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// Discard the pseudo instruction.
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MBB.erase(II);
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}
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void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const {
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// Get the instruction.
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MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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unsigned Reg = PPC::R0;
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unsigned SrcReg = MI.getOperand(0).getReg();
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BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
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.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
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addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
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.addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
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FrameIndex);
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// Discard the pseudo instruction.
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MBB.erase(II);
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}
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void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const {
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// Get the instruction.
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MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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// FIXME: Once LLVM supports creating virtual registers here, or the register
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// scavenger can return multiple registers, stop using reserved registers
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// here.
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unsigned Reg = PPC::R0;
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unsigned DestReg = MI.getOperand(0).getReg();
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assert(MI.definesRegister(DestReg) &&
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"RESTORE_VRSAVE does not define its destination");
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addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
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Reg), FrameIndex);
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BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
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.addReg(Reg);
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// Discard the pseudo instruction.
|
|
MBB.erase(II);
|
|
}
|
|
|
|
bool
|
|
PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|
unsigned Reg, int &FrameIdx) const {
|
|
|
|
// For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
|
|
// ABI, return true to prevent allocating an additional frame slot.
|
|
// For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
|
|
// is arbitrary and will be subsequently ignored. For 32-bit, we have
|
|
// previously created the stack slot if needed, so return its FrameIdx.
|
|
if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
|
|
if (Subtarget.isPPC64())
|
|
FrameIdx = 0;
|
|
else {
|
|
const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
FrameIdx = FI->getCRSpillFrameIndex();
|
|
}
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void
|
|
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, unsigned FIOperandNum,
|
|
RegScavenger *RS) const {
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
// Get the instruction.
|
|
MachineInstr &MI = *II;
|
|
// Get the instruction's basic block.
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
// Get the basic block's function.
|
|
MachineFunction &MF = *MBB.getParent();
|
|
// Get the frame info.
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
// Take into account whether it's an add or mem instruction
|
|
unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
|
|
if (MI.isInlineAsm())
|
|
OffsetOperandNo = FIOperandNum-1;
|
|
|
|
// Get the frame index.
|
|
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
|
|
|
// Get the frame pointer save index. Users of this index are primarily
|
|
// DYNALLOC instructions.
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
|
// Get the instruction opcode.
|
|
unsigned OpC = MI.getOpcode();
|
|
|
|
// Special case for dynamic alloca.
|
|
if (FPSI && FrameIndex == FPSI &&
|
|
(OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
|
|
lowerDynamicAlloc(II);
|
|
return;
|
|
}
|
|
|
|
// Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
|
|
if (OpC == PPC::SPILL_CR) {
|
|
lowerCRSpilling(II, FrameIndex);
|
|
return;
|
|
} else if (OpC == PPC::RESTORE_CR) {
|
|
lowerCRRestore(II, FrameIndex);
|
|
return;
|
|
} else if (OpC == PPC::SPILL_VRSAVE) {
|
|
lowerVRSAVESpilling(II, FrameIndex);
|
|
return;
|
|
} else if (OpC == PPC::RESTORE_VRSAVE) {
|
|
lowerVRSAVERestore(II, FrameIndex);
|
|
return;
|
|
}
|
|
|
|
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
|
|
|
bool is64Bit = Subtarget.isPPC64();
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
|
|
(is64Bit ? PPC::X31 : PPC::R31) :
|
|
(is64Bit ? PPC::X1 : PPC::R1),
|
|
false);
|
|
|
|
// Figure out if the offset in the instruction is shifted right two bits. This
|
|
// is true for instructions like "STD", which the machine implicitly adds two
|
|
// low zeros to.
|
|
bool isIXAddr = false;
|
|
switch (OpC) {
|
|
case PPC::LWA:
|
|
case PPC::LD:
|
|
case PPC::STD:
|
|
case PPC::STD_32:
|
|
isIXAddr = true;
|
|
break;
|
|
}
|
|
|
|
bool noImmForm = false;
|
|
switch (OpC) {
|
|
case PPC::LVEBX:
|
|
case PPC::LVEHX:
|
|
case PPC::LVEWX:
|
|
case PPC::LVX:
|
|
case PPC::LVXL:
|
|
case PPC::LVSL:
|
|
case PPC::LVSR:
|
|
case PPC::STVEBX:
|
|
case PPC::STVEHX:
|
|
case PPC::STVEWX:
|
|
case PPC::STVX:
|
|
case PPC::STVXL:
|
|
noImmForm = true;
|
|
break;
|
|
}
|
|
|
|
// Now add the frame object offset to the offset from r1.
|
|
int Offset = MFI->getObjectOffset(FrameIndex);
|
|
if (!isIXAddr)
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm();
|
|
else
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
|
|
|
|
// If we're not using a Frame Pointer that has been set to the value of the
|
|
// SP before having the stack size subtracted from it, then add the stack size
|
|
// to Offset to get the correct offset.
|
|
// Naked functions have stack size 0, although getStackSize may not reflect that
|
|
// because we didn't call all the pieces that compute it for naked functions.
|
|
if (!MF.getFunction()->getAttributes().
|
|
hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
|
|
Offset += MFI->getStackSize();
|
|
|
|
// If we can, encode the offset directly into the instruction. If this is a
|
|
// normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
|
|
// this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
|
|
// clear can be encoded. This is extremely uncommon, because normally you
|
|
// only "std" to a stack slot that is at least 4-byte aligned, but it can
|
|
// happen in invalid code.
|
|
if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
|
|
(!noImmForm &&
|
|
isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
|
|
if (isIXAddr)
|
|
Offset >>= 2; // The actual encoded value has the low two bits zero.
|
|
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
|
|
return;
|
|
}
|
|
|
|
// The offset doesn't fit into a single register, scavenge one to build the
|
|
// offset in.
|
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC);
|
|
|
|
// Insert a set of rA with the full offset value before the ld, st, or add
|
|
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
|
|
.addImm(Offset >> 16);
|
|
BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
|
|
.addReg(SReg, RegState::Kill)
|
|
.addImm(Offset);
|
|
|
|
// Convert into indexed form of the instruction:
|
|
//
|
|
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
|
|
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
|
|
unsigned OperandBase;
|
|
|
|
if (noImmForm)
|
|
OperandBase = 1;
|
|
else if (OpC != TargetOpcode::INLINEASM) {
|
|
assert(ImmToIdxMap.count(OpC) &&
|
|
"No indexed form of load or store available!");
|
|
unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
|
|
MI.setDesc(TII.get(NewOpcode));
|
|
OperandBase = 1;
|
|
} else {
|
|
OperandBase = OffsetOperandNo;
|
|
}
|
|
|
|
unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
|
|
MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
|
|
MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
if (!Subtarget.isPPC64())
|
|
return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
|
|
else
|
|
return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getEHExceptionRegister() const {
|
|
return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getEHHandlerRegister() const {
|
|
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
|
|
}
|