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Elena Demikhovsky 52981c4b60 I optimized the following patterns:
sext <4 x i1> to <4 x i64>
 sext <4 x i8> to <4 x i64>
 sext <4 x i16> to <4 x i64>
 
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
 (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
 
 The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
 The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.

I also added a cost of this operations to the AVX costs table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 12:42:54 +00:00
autoconf
bindings
cmake
docs Spelling corrections 2013-02-18 02:44:09 +00:00
examples
include Modify LiveInterval::addRange() to match the comment about what it returns. 2013-02-20 06:46:44 +00:00
lib I optimized the following patterns: 2013-02-20 12:42:54 +00:00
projects
runtime
test I optimized the following patterns: 2013-02-20 12:42:54 +00:00
tools [llvm-readobj] Add ELF .dynamic table dumping. 2013-02-20 02:37:12 +00:00
unittests Rename llvm::Optional<T>::Reset to 'reset' as per LLVM naming conventions. 2013-02-20 06:25:36 +00:00
utils
.arcconfig
.gitignore
CMakeLists.txt Revert CMake version bump since we don't actually need 2.8.6 any more. 2013-02-18 11:53:37 +00:00
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Low Level Virtual Machine (LLVM)
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