mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-06 21:05:51 +00:00
abcde265b1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.5 KiB
TableGen
48 lines
1.5 KiB
TableGen
//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
|
|
// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
|
|
// slot has been removed.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
def ALU_X : FuncUnit;
|
|
def ALU_Y : FuncUnit;
|
|
def ALU_Z : FuncUnit;
|
|
def ALU_W : FuncUnit;
|
|
def TRANS : FuncUnit;
|
|
|
|
def AnyALU : InstrItinClass;
|
|
def VecALU : InstrItinClass;
|
|
def TransALU : InstrItinClass;
|
|
|
|
def R600_VLIW5_Itin : ProcessorItineraries <
|
|
[ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL],
|
|
[],
|
|
[
|
|
InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
|
|
InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
|
|
InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
|
|
InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
|
|
]
|
|
>;
|
|
|
|
def R600_VLIW4_Itin : ProcessorItineraries <
|
|
[ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL],
|
|
[],
|
|
[
|
|
InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
|
|
InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
|
|
InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
|
|
InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
|
|
]
|
|
>;
|