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Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
204 lines
7.3 KiB
TableGen
204 lines
7.3 KiB
TableGen
//===- AArch64RegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains declarations that describe the AArch64 register file
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//
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//===----------------------------------------------------------------------===//
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let Namespace = "AArch64" in {
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def sub_128 : SubRegIndex<128>;
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def sub_64 : SubRegIndex<64>;
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def sub_32 : SubRegIndex<32>;
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def sub_16 : SubRegIndex<16>;
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def sub_8 : SubRegIndex<8>;
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// The VPR registers are handled as sub-registers of FPR equivalents, but
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// they're really the same thing. We give this concept a special index.
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def sub_alias : SubRegIndex<128>;
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}
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// Registers are identified with 5-bit ID numbers.
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class AArch64Reg<bits<16> enc, string n> : Register<n> {
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let HWEncoding = enc;
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let Namespace = "AArch64";
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}
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class AArch64RegWithSubs<bits<16> enc, string n, list<Register> subregs = [],
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list<SubRegIndex> inds = []>
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: AArch64Reg<enc, n> {
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let SubRegs = subregs;
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let SubRegIndices = inds;
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}
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//===----------------------------------------------------------------------===//
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// Integer registers: w0-w30, wzr, wsp, x0-x30, xzr, sp
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//===----------------------------------------------------------------------===//
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foreach Index = 0-30 in {
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def W#Index : AArch64Reg< Index, "w"#Index>, DwarfRegNum<[Index]>;
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}
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def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
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def WZR : AArch64Reg<31, "wzr">;
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// Could be combined with previous loop, but this way leaves w and x registers
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// consecutive as LLVM register numbers, which makes for easier debugging.
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foreach Index = 0-30 in {
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def X#Index : AArch64RegWithSubs<Index, "x"#Index,
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[!cast<Register>("W"#Index)], [sub_32]>,
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DwarfRegNum<[Index]>;
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}
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def XSP : AArch64RegWithSubs<31, "sp", [WSP], [sub_32]>, DwarfRegNum<[31]>;
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def XZR : AArch64RegWithSubs<31, "xzr", [WZR], [sub_32]>;
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// Most instructions treat register 31 as zero for reads and a black-hole for
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// writes.
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// Note that the order of registers is important for the Disassembler here:
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// tablegen uses it to form MCRegisterClass::getRegister, which we assume can
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// take an encoding value.
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def GPR32 : RegisterClass<"AArch64", [i32], 32,
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(add (sequence "W%u", 0, 30), WZR)> {
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}
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def GPR64 : RegisterClass<"AArch64", [i64], 64,
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(add (sequence "X%u", 0, 30), XZR)> {
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}
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def GPR32nowzr : RegisterClass<"AArch64", [i32], 32,
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(sequence "W%u", 0, 30)> {
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}
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def GPR64noxzr : RegisterClass<"AArch64", [i64], 64,
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(sequence "X%u", 0, 30)> {
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}
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// For tail calls, we can't use callee-saved registers or the structure-return
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// register, as they are supposed to be live across function calls and may be
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// clobbered by the epilogue.
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def tcGPR64 : RegisterClass<"AArch64", [i64], 64,
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(add (sequence "X%u", 0, 7),
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(sequence "X%u", 9, 18))> {
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}
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// Certain addressing-useful instructions accept sp directly. Again the order of
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// registers is important to the Disassembler.
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def GPR32wsp : RegisterClass<"AArch64", [i32], 32,
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(add (sequence "W%u", 0, 30), WSP)> {
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}
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def GPR64xsp : RegisterClass<"AArch64", [i64], 64,
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(add (sequence "X%u", 0, 30), XSP)> {
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}
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// Some aliases *only* apply to SP (e.g. MOV uses different encoding for SP and
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// non-SP variants). We can't use a bare register in those patterns because
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// TableGen doesn't like it, so we need a class containing just stack registers
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def Rxsp : RegisterClass<"AArch64", [i64], 64,
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(add XSP)> {
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}
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def Rwsp : RegisterClass<"AArch64", [i32], 32,
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(add WSP)> {
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}
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//===----------------------------------------------------------------------===//
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// Scalar registers in the vector unit:
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// b0-b31, h0-h31, s0-s31, d0-d31, q0-q31
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//===----------------------------------------------------------------------===//
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foreach Index = 0-31 in {
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def B # Index : AArch64Reg< Index, "b" # Index>,
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DwarfRegNum<[!add(Index, 64)]>;
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def H # Index : AArch64RegWithSubs<Index, "h" # Index,
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[!cast<Register>("B" # Index)], [sub_8]>,
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DwarfRegNum<[!add(Index, 64)]>;
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def S # Index : AArch64RegWithSubs<Index, "s" # Index,
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[!cast<Register>("H" # Index)], [sub_16]>,
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DwarfRegNum<[!add(Index, 64)]>;
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def D # Index : AArch64RegWithSubs<Index, "d" # Index,
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[!cast<Register>("S" # Index)], [sub_32]>,
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DwarfRegNum<[!add(Index, 64)]>;
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def Q # Index : AArch64RegWithSubs<Index, "q" # Index,
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[!cast<Register>("D" # Index)], [sub_64]>,
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DwarfRegNum<[!add(Index, 64)]>;
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}
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def FPR8 : RegisterClass<"AArch64", [i8], 8,
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(sequence "B%u", 0, 31)> {
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}
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def FPR16 : RegisterClass<"AArch64", [f16], 16,
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(sequence "H%u", 0, 31)> {
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}
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def FPR32 : RegisterClass<"AArch64", [f32], 32,
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(sequence "S%u", 0, 31)> {
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}
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def FPR64 : RegisterClass<"AArch64", [f64], 64,
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(sequence "D%u", 0, 31)> {
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}
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def FPR128 : RegisterClass<"AArch64", [f128], 128,
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(sequence "Q%u", 0, 31)> {
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}
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//===----------------------------------------------------------------------===//
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// Vector registers:
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//===----------------------------------------------------------------------===//
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// NEON registers simply specify the overall vector, and it's expected that
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// Instructions will individually specify the acceptable data layout. In
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// principle this leaves two approaches open:
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// + An operand, giving a single ADDvvv instruction (for example). This turns
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// out to be unworkable in the assembly parser (without every Instruction
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// having a "cvt" function, at least) because the constraints can't be
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// properly enforced. It also complicates specifying patterns since each
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// instruction will accept many types.
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// + A bare token (e.g. ".2d"). This means the AsmParser has to know specific
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// details about NEON registers, but simplifies most other details.
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//
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// The second approach was taken.
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foreach Index = 0-31 in {
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def V # Index : AArch64RegWithSubs<Index, "v" # Index,
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[!cast<Register>("Q" # Index)],
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[sub_alias]>,
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DwarfRegNum<[!add(Index, 64)]>;
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}
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// These two classes contain the same registers, which should be reasonably
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// sensible for MC and allocation purposes, but allows them to be treated
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// separately for things like stack spilling.
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def VPR64 : RegisterClass<"AArch64", [v2f32, v2i32, v4i16, v8i8, v1i64], 64,
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(sequence "V%u", 0, 31)>;
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def VPR128 : RegisterClass<"AArch64",
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[v2f64, v2i64, v4f32, v4i32, v8i16, v16i8], 128,
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(sequence "V%u", 0, 31)>;
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// Flags register
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def NZCV : Register<"nzcv"> {
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let Namespace = "AArch64";
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}
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def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
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let CopyCost = -1;
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let isAllocatable = 0;
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}
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