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https://github.com/c64scene-ar/llvm-6502.git
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c3cee57f7d
We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.6 KiB
C++
73 lines
2.6 KiB
C++
//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Mips specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSMCTARGETDESC_H
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#define MIPSMCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class StringRef;
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class Target;
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class raw_ostream;
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extern Target TheMipsTarget;
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extern Target TheMipselTarget;
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extern Target TheMips64Target;
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extern Target TheMips64elTarget;
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MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS,
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uint8_t OSABI,
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bool IsLittleEndian,
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bool Is64Bit);
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} // End llvm namespace
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// Defines symbolic names for Mips registers. This defines a mapping from
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// register name to register number.
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#define GET_REGINFO_ENUM
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#include "MipsGenRegisterInfo.inc"
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// Defines symbolic names for the Mips instructions.
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#define GET_INSTRINFO_ENUM
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#include "MipsGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "MipsGenSubtargetInfo.inc"
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#endif
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