mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.7 KiB
C++
45 lines
1.7 KiB
C++
//===--------------------- AMDGPUFrameLowering.h ----------------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief Interface to describe a layout of a stack frame on a AMDIL target
|
|
/// machine.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
#ifndef AMDILFRAME_LOWERING_H
|
|
#define AMDILFRAME_LOWERING_H
|
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
#include "llvm/Target/TargetFrameLowering.h"
|
|
|
|
namespace llvm {
|
|
|
|
/// \brief Information about the stack frame layout on the AMDGPU targets.
|
|
///
|
|
/// It holds the direction of the stack growth, the known stack alignment on
|
|
/// entry to each function, and the offset to the locals area.
|
|
/// See TargetFrameInfo for more comments.
|
|
class AMDGPUFrameLowering : public TargetFrameLowering {
|
|
public:
|
|
AMDGPUFrameLowering(StackDirection D, unsigned StackAl, int LAO,
|
|
unsigned TransAl = 1);
|
|
virtual ~AMDGPUFrameLowering();
|
|
|
|
/// \returns The number of 32-bit sub-registers that are used when storing
|
|
/// values to the stack.
|
|
virtual unsigned getStackWidth(const MachineFunction &MF) const;
|
|
virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
|
|
virtual const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) const;
|
|
virtual void emitPrologue(MachineFunction &MF) const;
|
|
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
|
virtual bool hasFP(const MachineFunction &MF) const;
|
|
};
|
|
} // namespace llvm
|
|
#endif // AMDILFRAME_LOWERING_H
|