mirror of
https://github.com/c64scene-ar/llvm-6502.git
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04c559569f
The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.7 KiB
CMake
58 lines
1.7 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
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tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
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tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
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tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
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add_public_tablegen_target(AMDGPUCommonTableGen)
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add_llvm_target(R600CodeGen
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AMDILCFGStructurizer.cpp
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AMDILIntrinsicInfo.cpp
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AMDILISelLowering.cpp
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AMDGPUAsmPrinter.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUISelDAGToDAG.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUSubtarget.cpp
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AMDGPUTargetMachine.cpp
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AMDGPUTargetTransformInfo.cpp
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AMDGPUISelLowering.cpp
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AMDGPUConvertToISA.cpp
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AMDGPUInstrInfo.cpp
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AMDGPURegisterInfo.cpp
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrInfo.cpp
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600TextureIntrinsicsReplacer.cpp
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SIAnnotateControlFlow.cpp
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SIFixSGPRCopies.cpp
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SIInsertWaits.cpp
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SIInstrInfo.cpp
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SIISelLowering.cpp
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SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIRegisterInfo.cpp
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SITypeRewriter.cpp
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)
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add_dependencies(LLVMR600CodeGen AMDGPUCommonTableGen intrinsics_gen)
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add_subdirectory(InstPrinter)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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