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f95b162188
The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
3.3 KiB
C++
77 lines
3.3 KiB
C++
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIISELLOWERING_H
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#define SIISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class SITargetLowering : public AMDGPUTargetLowering {
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SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
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SDValue Chain, unsigned Offset) const;
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SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
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SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue ResourceDescriptorToi128(SDValue Op, SelectionDAG &DAG) const;
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bool foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const;
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const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
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const SDValue &Op) const;
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bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const;
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void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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unsigned RegClass, bool &ScalarSlotUsed) const;
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SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
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void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
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MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
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public:
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SITargetLowering(TargetMachine &tm);
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bool allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const;
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virtual bool shouldSplitVectorElementType(EVT VT) const;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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MachineBasicBlock * BB) const;
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virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
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virtual MVT getScalarShiftAmountTy(EVT VT) const;
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virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
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virtual void AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const;
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int32_t analyzeImmediate(const SDNode *N) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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};
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} // End namespace llvm
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#endif //SIISELLOWERING_H
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