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04c559569f
The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.4 KiB
C++
103 lines
3.4 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIINSTRINFO_H
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#define SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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const SIRegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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unsigned commuteOpcode(unsigned Opcode) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI=false) const;
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virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
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MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const;
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virtual bool isMov(unsigned Opcode) const;
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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int isMIMG(uint16_t Opcode) const;
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int isSMRD(uint16_t Opcode) const;
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bool isVOP1(uint16_t Opcode) const;
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bool isVOP2(uint16_t Opcode) const;
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bool isVOP3(uint16_t Opcode) const;
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bool isVOPC(uint16_t Opcode) const;
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bool isInlineConstant(const MachineOperand &MO) const;
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bool isLiteralConstant(const MachineOperand &MO) const;
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virtual bool verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const;
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virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
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virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
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virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const;
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virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
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virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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};
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namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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} // End namespace AMDGPU
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} // End namespace llvm
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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}
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#endif //SIINSTRINFO_H
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