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- vec_const.ll: Vector constant loads - immed64.ll: i64, f64 constant loads git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45242 91177308-0d34-0410-b5e6-96231b3b80d8
184 lines
5.1 KiB
C++
184 lines
5.1 KiB
C++
//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by a team from the Computer Systems Research
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// Department at The Aerospace Corporation and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Cell SPU implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SPURegisterNames.h"
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#include "SPUInstrInfo.h"
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#include "SPUTargetMachine.h"
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#include "SPUGenInstrInfo.inc"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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: TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
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TM(tm),
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RI(*TM.getSubtargetImpl(), *this)
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{
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/* NOP */
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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SPUInstrInfo::getPointerRegClass() const
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{
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return &SPU::R32CRegClass;
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}
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bool
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SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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// Primarily, ORI and OR are generated by copyRegToReg. But, there are other
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// cases where we can safely say that what's being done is really a move
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// (see how PowerPC does this -- it's the model for this code too.)
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switch (MI.getOpcode()) {
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default:
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break;
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case SPU::ORIv4i32:
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case SPU::ORIr32:
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case SPU::ORIr64:
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case SPU::ORHIv8i16:
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case SPU::ORHIr16:
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case SPU::ORHI1To2:
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case SPU::ORBIv16i8:
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case SPU::ORBIr8:
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case SPU::ORI2To4:
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case SPU::ORI1To4:
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case SPU::AHIvec:
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case SPU::AHIr16:
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case SPU::AIvec:
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
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if (MI.getOperand(2).getImmedValue() == 0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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case SPU::AIr32:
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assert(MI.getNumOperands() == 3 &&
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"wrong number of operands to AIr32");
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if (MI.getOperand(0).isRegister() &&
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(MI.getOperand(1).isRegister() ||
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MI.getOperand(1).isFrameIndex()) &&
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(MI.getOperand(2).isImmediate() &&
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MI.getOperand(2).getImmedValue() == 0)) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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case SPU::ORv16i8_i8:
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case SPU::ORv8i16_i16:
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case SPU::ORv4i32_i32:
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case SPU::ORv2i64_i64:
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case SPU::ORv4f32_f32:
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case SPU::ORv2f64_f64:
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case SPU::ORi8_v16i8:
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case SPU::ORi16_v8i16:
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case SPU::ORi32_v4i32:
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case SPU::ORi64_v2i64:
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case SPU::ORf32_v4f32:
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case SPU::ORf64_v2f64:
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case SPU::ORv16i8:
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case SPU::ORv8i16:
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case SPU::ORv4i32:
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case SPU::ORr32:
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case SPU::ORr64:
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case SPU::ORf32:
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case SPU::ORf64:
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case SPU::ORgprc:
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid SPU OR(vec|r32|r64|gprc) instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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break;
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}
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return false;
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}
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unsigned
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SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SPU::LQDv16i8:
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case SPU::LQDv8i16:
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case SPU::LQDv4i32:
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case SPU::LQDv4f32:
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case SPU::LQDv2f64:
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case SPU::LQDr128:
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case SPU::LQDr64:
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case SPU::LQDr32:
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case SPU::LQDr16:
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case SPU::LQXv4i32:
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case SPU::LQXr128:
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case SPU::LQXr64:
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case SPU::LQXr32:
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case SPU::LQXr16:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned
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SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SPU::STQDv16i8:
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case SPU::STQDv8i16:
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case SPU::STQDv4i32:
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case SPU::STQDv4f32:
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case SPU::STQDv2f64:
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case SPU::STQDr128:
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case SPU::STQDr64:
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case SPU::STQDr32:
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case SPU::STQDr16:
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// case SPU::STQDr8:
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case SPU::STQXv16i8:
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case SPU::STQXv8i16:
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case SPU::STQXv4i32:
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case SPU::STQXv4f32:
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case SPU::STQXv2f64:
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case SPU::STQXr128:
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case SPU::STQXr64:
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case SPU::STQXr32:
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case SPU::STQXr16:
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// case SPU::STQXr8:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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