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https://github.com/c64scene-ar/llvm-6502.git
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12745c55e1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6323 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
3.1 KiB
C++
82 lines
3.1 KiB
C++
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES)
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#define IMPREGSLIST(NAME, ...) \
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static const unsigned NAME[] = { __VA_ARGS__ };
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#include "X86InstrInfo.def"
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// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
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// descriptors
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//
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static const TargetInstrDescriptor X86Insts[] = {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPUSES, IMPDEFS) \
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{ NAME, \
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-1, /* Always vararg */ \
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((TSFLAGS) & X86II::Void) ? -1 : 0, /* Result is in 0 */ \
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0, /* maxImmedConst field */\
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false, /* immedIsSignExtended */\
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0, /* numDelaySlots */\
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0, /* latency */\
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0, /* schedClass */\
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FLAGS, /* Flags */\
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TSFLAGS, /* TSFlags */\
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IMPUSES, /* ImplicitUses */\
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IMPDEFS }, /* ImplicitDefs */
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#include "X86InstrInfo.def"
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};
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X86InstrInfo::X86InstrInfo()
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: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
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}
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// createNOPinstr - returns the target's implementation of NOP, which is
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// usually a pseudo-instruction, implemented by a degenerate version of
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// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
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//
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MachineInstr* X86InstrInfo::createNOPinstr() const {
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return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX).addReg(X86::AX);
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}
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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//
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bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `xchg ax, ax'
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if (MI.getOpcode() == X86::XCHGrr16 && MI.getNumOperands() == 2) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
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op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX)
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{
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return true;
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}
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}
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return false;
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}
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static unsigned char BaseOpcodes[] = {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) BASEOPCODE,
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#include "X86InstrInfo.def"
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};
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified opcode number.
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//
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unsigned char X86InstrInfo::getBaseOpcodeFor(unsigned Opcode) const {
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assert(Opcode < sizeof(BaseOpcodes)/sizeof(BaseOpcodes[0]) &&
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"Opcode out of range!");
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return BaseOpcodes[Opcode];
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}
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