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bacf9f4888
isel changes happened months ago. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31164 91177308-0d34-0410-b5e6-96231b3b80d8
586 lines
22 KiB
C++
586 lines
22 KiB
C++
//===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for IA64,
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// converting a legalized dag to an IA64 dag.
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//
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//===----------------------------------------------------------------------===//
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#include "IA64.h"
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#include "IA64TargetMachine.h"
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#include "IA64ISelLowering.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <iostream>
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#include <queue>
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#include <set>
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using namespace llvm;
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namespace {
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Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
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Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
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/// instructions for SelectionDAG operations.
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///
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class IA64DAGToDAGISel : public SelectionDAGISel {
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IA64TargetLowering IA64Lowering;
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unsigned GlobalBaseReg;
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public:
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IA64DAGToDAGISel(IA64TargetMachine &TM)
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: SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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return SelectionDAGISel::runOnFunction(Fn);
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}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
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// SDOperand getGlobalBaseReg(); TODO: hmm
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDNode *Select(SDOperand N);
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SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic = false,
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bool Negate = false);
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SDNode *SelectBitfieldInsert(SDNode *N);
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/// SelectCC - Select a comparison of the specified values with the
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/// specified condition code, returning the CR# of the expression.
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SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
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/// SelectAddr - Given the specified address, return the two operands for a
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/// load/store instruction, and return true if it should be an indexed [r+r]
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/// operation.
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bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "IA64 (Itanium) DAG->DAG Instruction Selector";
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}
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// Include the pieces autogenerated from the target description.
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#include "IA64GenDAGISel.inc"
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private:
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SDNode *SelectDIV(SDOperand Op);
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand Chain = N->getOperand(0);
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SDOperand Tmp1 = N->getOperand(0);
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SDOperand Tmp2 = N->getOperand(1);
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AddToISelQueue(Chain);
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AddToISelQueue(Tmp1);
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AddToISelQueue(Tmp2);
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bool isFP=false;
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if(MVT::isFloatingPoint(Tmp1.getValueType()))
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isFP=true;
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bool isModulus=false; // is it a division or a modulus?
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bool isSigned=false;
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switch(N->getOpcode()) {
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case ISD::FDIV:
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case ISD::SDIV: isModulus=false; isSigned=true; break;
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case ISD::UDIV: isModulus=false; isSigned=false; break;
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case ISD::FREM:
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case ISD::SREM: isModulus=true; isSigned=true; break;
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case ISD::UREM: isModulus=true; isSigned=false; break;
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}
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// TODO: check for integer divides by powers of 2 (or other simple patterns?)
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SDOperand TmpPR, TmpPR2;
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SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
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SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
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SDNode *Result;
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// we'll need copies of F0 and F1
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SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
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SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
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// OK, emit some code:
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if(!isFP) {
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// first, load the inputs into FP regs.
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TmpF1 =
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SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
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Chain = TmpF1.getValue(1);
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TmpF2 =
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SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
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Chain = TmpF2.getValue(1);
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// next, convert the inputs to FP
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if(isSigned) {
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TmpF3 =
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SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
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Chain = TmpF3.getValue(1);
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TmpF4 =
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SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
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Chain = TmpF4.getValue(1);
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} else { // is unsigned
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TmpF3 =
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SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
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Chain = TmpF3.getValue(1);
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TmpF4 =
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SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
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Chain = TmpF4.getValue(1);
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}
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} else { // this is an FP divide/remainder, so we 'leak' some temp
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// regs and assign TmpF3=Tmp1, TmpF4=Tmp2
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TmpF3=Tmp1;
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TmpF4=Tmp2;
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}
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// we start by computing an approximate reciprocal (good to 9 bits?)
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// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
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if(isFP)
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TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
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TmpF3, TmpF4), 0);
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else
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TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
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TmpF3, TmpF4), 0);
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TmpPR = TmpF5.getValue(1);
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Chain = TmpF5.getValue(2);
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SDOperand minusB;
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if(isModulus) { // for remainders, it'll be handy to have
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// copies of -input_b
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minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
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CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
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Chain = minusB.getValue(1);
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}
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SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
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SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
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TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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OpsE0, 4), 0);
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Chain = TmpE0.getValue(1);
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SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
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TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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OpsY1, 4), 0);
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Chain = TmpY1.getValue(1);
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SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
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TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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OpsE1, 4), 0);
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Chain = TmpE1.getValue(1);
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SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
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TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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OpsY2, 4), 0);
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Chain = TmpY2.getValue(1);
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if(isFP) { // if this is an FP divide, we finish up here and exit early
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if(isModulus)
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assert(0 && "Sorry, try another FORTRAN compiler.");
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SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
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SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
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TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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OpsE2, 4), 0);
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Chain = TmpE2.getValue(1);
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SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
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TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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OpsY3, 4), 0);
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Chain = TmpY3.getValue(1);
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SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
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TmpQ0 =
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SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
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OpsQ0, 4), 0);
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Chain = TmpQ0.getValue(1);
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SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
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TmpR0 =
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SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
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OpsR0, 4), 0);
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Chain = TmpR0.getValue(1);
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// we want Result to have the same target register as the frcpa, so
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// we two-address hack it. See the comment "for this to work..." on
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// page 48 of Intel application note #245415
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SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
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Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
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Ops, 5);
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Chain = SDOperand(Result, 1);
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return Result; // XXX: early exit!
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} else { // this is *not* an FP divide, so there's a bit left to do:
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SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
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SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
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TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
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OpsQ2, 4), 0);
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Chain = TmpQ2.getValue(1);
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SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
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TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
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OpsR2, 4), 0);
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Chain = TmpR2.getValue(1);
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// we want TmpQ3 to have the same target register as the frcpa? maybe we
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// should two-address hack it. See the comment "for this to work..." on page
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// 48 of Intel application note #245415
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SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
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TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
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OpsQ3, 5), 0);
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Chain = TmpQ3.getValue(1);
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// STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
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// the FPSWA won't be able to help out in the case of large/tiny
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// arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
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if(isSigned)
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TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
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MVT::f64, TmpQ3), 0);
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else
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TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
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MVT::f64, TmpQ3), 0);
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Chain = TmpQ.getValue(1);
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if(isModulus) {
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SDOperand FPminusB =
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SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
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Chain = FPminusB.getValue(1);
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SDOperand Remainder =
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SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
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TmpQ, FPminusB, TmpF1), 0);
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Chain = Remainder.getValue(1);
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
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Chain = SDOperand(Result, 1);
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} else { // just an integer divide
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Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
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Chain = SDOperand(Result, 1);
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}
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return Result;
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} // wasn't an FP divide
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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N->getOpcode() < IA64ISD::FIRST_NUMBER)
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return NULL; // Already selected.
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switch (N->getOpcode()) {
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default: break;
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case IA64ISD::BRCALL: { // XXX: this is also a hack!
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SDOperand Chain = N->getOperand(0);
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SDOperand InFlag; // Null incoming flag value.
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AddToISelQueue(Chain);
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if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
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InFlag = N->getOperand(2);
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AddToISelQueue(InFlag);
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}
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unsigned CallOpcode;
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SDOperand CallOperand;
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// if we can call directly, do so
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
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CallOpcode = IA64::BRCALL_IPREL_GA;
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CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
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} else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
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// case for correctness, to avoid
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// "non-pic code with imm reloc.n
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// against dynamic symbol" errors
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dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
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CallOpcode = IA64::BRCALL_IPREL_ES;
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CallOperand = N->getOperand(1);
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} else {
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// otherwise we need to load the function descriptor,
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// load the branch target (function)'s entry point and GP,
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// branch (call) then restore the GP
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SDOperand FnDescriptor = N->getOperand(1);
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AddToISelQueue(FnDescriptor);
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// load the branch target's entry point [mem] and
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// GP value [mem+8]
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SDOperand targetEntryPoint=
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SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
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Chain = targetEntryPoint.getValue(1);
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SDOperand targetGPAddr=
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SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
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FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
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Chain = targetGPAddr.getValue(1);
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SDOperand targetGP=
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SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
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Chain = targetGP.getValue(1);
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Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
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InFlag = Chain.getValue(1);
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Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
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InFlag = Chain.getValue(1);
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CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
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CallOpcode = IA64::BRCALL_INDIRECT;
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}
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// Finally, once everything is setup, emit the call itself
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if(InFlag.Val)
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Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
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CallOperand, InFlag), 0);
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else // there might be no arguments
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Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
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CallOperand, Chain), 0);
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InFlag = Chain.getValue(1);
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std::vector<SDOperand> CallResults;
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CallResults.push_back(Chain);
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CallResults.push_back(InFlag);
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for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
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ReplaceUses(Op.getValue(i), CallResults[i]);
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return NULL;
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}
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case IA64ISD::GETFD: {
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SDOperand Input = N->getOperand(0);
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AddToISelQueue(Input);
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return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
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}
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case ISD::FDIV:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM:
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return SelectDIV(Op);
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case ISD::TargetConstantFP: {
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SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
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SDOperand V;
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if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
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V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
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} else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
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V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
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} else
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assert(0 && "Unexpected FP constant!");
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|
|
ReplaceUses(SDOperand(N, 0), V);
|
|
return 0;
|
|
}
|
|
|
|
case ISD::FrameIndex: { // TODO: reduce creepyness
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
|
if (N->hasOneUse())
|
|
return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
|
|
CurDAG->getTargetFrameIndex(FI, MVT::i64));
|
|
else
|
|
return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
|
|
CurDAG->getTargetFrameIndex(FI, MVT::i64));
|
|
}
|
|
|
|
case ISD::ConstantPool: { // TODO: nuke the constant pool
|
|
// (ia64 doesn't need one)
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
|
|
Constant *C = CP->getConstVal();
|
|
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
|
|
CP->getAlignment());
|
|
return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
|
|
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
|
|
}
|
|
|
|
case ISD::GlobalAddress: {
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
|
|
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
|
|
SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
|
|
CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
|
|
return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
|
|
}
|
|
|
|
/* XXX case ISD::ExternalSymbol: {
|
|
SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
|
|
MVT::i64);
|
|
SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
|
|
CurDAG->getRegister(IA64::r1, MVT::i64), EA);
|
|
return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
|
|
}
|
|
*/
|
|
|
|
case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
SDOperand Chain = LD->getChain();
|
|
SDOperand Address = LD->getBasePtr();
|
|
AddToISelQueue(Chain);
|
|
AddToISelQueue(Address);
|
|
|
|
MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
|
|
unsigned Opc;
|
|
switch (TypeBeingLoaded) {
|
|
default:
|
|
#ifndef NDEBUG
|
|
N->dump();
|
|
#endif
|
|
assert(0 && "Cannot load this type!");
|
|
case MVT::i1: { // this is a bool
|
|
Opc = IA64::LD1; // first we load a byte, then compare for != 0
|
|
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
|
|
return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
|
|
SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
|
|
CurDAG->getRegister(IA64::r0, MVT::i64),
|
|
Chain);
|
|
}
|
|
/* otherwise, we want to load a bool into something bigger: LD1
|
|
will do that for us, so we just fall through */
|
|
}
|
|
case MVT::i8: Opc = IA64::LD1; break;
|
|
case MVT::i16: Opc = IA64::LD2; break;
|
|
case MVT::i32: Opc = IA64::LD4; break;
|
|
case MVT::i64: Opc = IA64::LD8; break;
|
|
|
|
case MVT::f32: Opc = IA64::LDF4; break;
|
|
case MVT::f64: Opc = IA64::LDF8; break;
|
|
}
|
|
|
|
// TODO: comment this
|
|
return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
|
|
Address, Chain);
|
|
}
|
|
|
|
case ISD::STORE: {
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
SDOperand Address = ST->getBasePtr();
|
|
SDOperand Chain = ST->getChain();
|
|
AddToISelQueue(Address);
|
|
AddToISelQueue(Chain);
|
|
|
|
unsigned Opc;
|
|
if (ISD::isNON_TRUNCStore(N)) {
|
|
switch (N->getOperand(1).getValueType()) {
|
|
default: assert(0 && "unknown type in store");
|
|
case MVT::i1: { // this is a bool
|
|
Opc = IA64::ST1; // we store either 0 or 1 as a byte
|
|
// first load zero!
|
|
SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
|
|
Chain = Initial.getValue(1);
|
|
// then load 1 into the same reg iff the predicate to store is 1
|
|
SDOperand Tmp = ST->getValue();
|
|
AddToISelQueue(Tmp);
|
|
Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
|
|
CurDAG->getConstant(1, MVT::i64),
|
|
Tmp), 0);
|
|
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
|
|
}
|
|
case MVT::i64: Opc = IA64::ST8; break;
|
|
case MVT::f64: Opc = IA64::STF8; break;
|
|
}
|
|
} else { // Truncating store
|
|
switch(ST->getStoredVT()) {
|
|
default: assert(0 && "unknown type in truncstore");
|
|
case MVT::i8: Opc = IA64::ST1; break;
|
|
case MVT::i16: Opc = IA64::ST2; break;
|
|
case MVT::i32: Opc = IA64::ST4; break;
|
|
case MVT::f32: Opc = IA64::STF4; break;
|
|
}
|
|
}
|
|
|
|
SDOperand N1 = N->getOperand(1);
|
|
SDOperand N2 = N->getOperand(2);
|
|
AddToISelQueue(N1);
|
|
AddToISelQueue(N2);
|
|
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
|
|
}
|
|
|
|
case ISD::BRCOND: {
|
|
SDOperand Chain = N->getOperand(0);
|
|
SDOperand CC = N->getOperand(1);
|
|
AddToISelQueue(Chain);
|
|
AddToISelQueue(CC);
|
|
MachineBasicBlock *Dest =
|
|
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
|
|
//FIXME - we do NOT need long branches all the time
|
|
return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
|
|
CurDAG->getBasicBlock(Dest), Chain);
|
|
}
|
|
|
|
case ISD::CALLSEQ_START:
|
|
case ISD::CALLSEQ_END: {
|
|
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
|
|
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
|
|
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
|
|
SDOperand N0 = N->getOperand(0);
|
|
AddToISelQueue(N0);
|
|
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
|
|
}
|
|
|
|
case ISD::BR:
|
|
// FIXME: we don't need long branches all the time!
|
|
SDOperand N0 = N->getOperand(0);
|
|
AddToISelQueue(N0);
|
|
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
|
|
N->getOperand(1), N0);
|
|
}
|
|
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
|
|
/// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
|
|
/// into an IA64-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass
|
|
*llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
|
|
return new IA64DAGToDAGISel(TM);
|
|
}
|
|
|