llvm-6502/test/CodeGen/Mips
Reed Kotler c1fe3e3b33 Fix two issues regarding Got pointer (GP) setup.
1) make sure that the first two instructions of the sequence cannot
separate from each other. The linker requires that they be sequential.
If they get separated, it can still work but it will not work in all
cases because the first of the instructions mostly involves the hi part
of the pc relative offset and that part changes slowly. You would have
to be at the right boundary for this to matter.
2) make sure that this sequence begins  on a longword boundary. 
There appears to be a bug in binutils which makes some of these calculations
get messed up if the instruction sequence does not begin on a longword
boundary. This is being investigated with the appropriate binutils folks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-18 22:46:09 +00:00
..
msa [mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518. 2013-09-11 12:39:25 +00:00
2008-06-05-Carry.ll
2008-07-03-SRet.ll
2008-07-06-fadd64.ll
2008-07-07-Float2Int.ll
2008-07-07-FPExtend.ll
2008-07-07-IntDoubleConvertions.ll
2008-07-15-InternalConstant.ll
2008-07-15-SmallSection.ll
2008-07-16-SignExtInReg.ll
2008-07-22-Cstpool.ll
2008-07-23-fpcmp.ll
2008-07-29-icmp.ll
2008-07-31-fcopysign.ll
2008-08-01-AsmInline.ll
2008-08-03-fabs64.ll
2008-08-03-ReturnDouble.ll
2008-08-04-Bitconvert.ll
2008-08-06-Alloca.ll
2008-08-07-CC.ll
2008-08-07-FPRound.ll
2008-08-08-bswap.ll
2008-08-08-ctlz.ll
2008-10-13-LegalizerBug.ll
2008-11-10-xint_to_fp.ll
2009-11-16-CstPoolLoad.ll
2010-07-20-Switch.ll
2010-11-09-CountLeading.ll
2010-11-09-Mul.ll
2011-05-26-BranchKillsVreg.ll
2012-12-12-ExpandMemcpy.ll
addc.ll
addi.ll
addressing-mode.ll
align16.ll
alloca16.ll
alloca.ll
analyzebranch.ll
and1.ll
asm-large-immediate.ll
atomic.ll
atomicops.ll
biggot.ll
blez_bgez.ll
blockaddr.ll
br-jmp.ll
brconeq.ll
brconeqk.ll
brconeqz.ll
brconge.ll
brcongt.ll
brconle.ll
brconlt.ll
brconne.ll
brconnek.ll
brconnez.ll
brdelayslot.ll
brind.ll
bswap.ll
buildpairextractelementf64.ll
check-noat.ll
cmov.ll
cmplarge.ll
const-mult.ll
constantfp0.ll
cprestore.ll
ctlz.ll
DbgValueOtherTargets.test
div_rem.ll
div.ll
divrem.ll
divu_remu.ll
divu.ll
double2int.ll
dsp-patterns-cmp-vselect.ll
dsp-patterns.ll
dsp-r1.ll
dsp-r2.ll
dsp-vec-load-store.ll
eh-dwarf-cfa.ll
eh-return32.ll
eh-return64.ll
eh.ll
emit-big-cst.ll
ex2.ll
extins.ll
f16abs.ll
fabs.ll
fastcc.ll
fcopysign-f32-f64.ll
fcopysign.ll
fixdfsf.ll
fmadd1.ll
fneg.ll
fp16instrinsmc.ll
fp16mix.ll Expand the mask capability for deciding which functions are mips16 and mips32 2013-09-15 02:09:08 +00:00
fp16static.ll
fp-indexed-ls.ll
fp-spill-reload.ll
fpbr.ll
fpneeded.ll
fpnotneeded.ll
frame-address.ll
frem.ll
global-address.ll
global-pointer-reg.ll
gpreg-lazy-binding.ll
gprestore.ll
helloworld.ll Fix two issues regarding Got pointer (GP) setup. 2013-09-18 22:46:09 +00:00
hf16_1.ll
hf16call32_body.ll
hf16call32.ll
hfptrcall.ll
i32k.ll
i64arg.ll
imm.ll
indirectcall.ll
init-array.ll
inlineasm64.ll
inlineasm_constraint.ll
inlineasm-cnstrnt-bad-I-1.ll
inlineasm-cnstrnt-bad-J.ll
inlineasm-cnstrnt-bad-K.ll
inlineasm-cnstrnt-bad-L.ll
inlineasm-cnstrnt-bad-N.ll
inlineasm-cnstrnt-bad-O.ll
inlineasm-cnstrnt-bad-P.ll
inlineasm-cnstrnt-reg64.ll
inlineasm-cnstrnt-reg.ll
inlineasm-operand-code.ll
inlineasmmemop.ll
int-to-float-conversion.ll
internalfunc.ll
jtstat.ll
largefr1.ll
largeimm1.ll
largeimmprinting.ll
lb1.ll
lbu1.ll
lh1.ll
lhu1.ll
lit.local.cfg
llcarry.ll
load-store-left-right.ll
longbranch.ll
machineverifier.ll
madd-msub.ll
memcpy.ll
mips16_32_1.ll
mips16_32_3.ll
mips16_32_4.ll
mips16_32_5.ll
mips16_32_6.ll
mips16_32_7.ll
mips16_32_8.ll
mips16_32_9.ll
mips16_32_10.ll
mips16_fpret.ll
mips16ex.ll
mips16fpe.ll
mips64-f128-call.ll
mips64-f128.ll
mips64-fp-indexed-ls.ll
mips64-libcall.ll
mips64-sret.ll
mips64countleading.ll
mips64directive.ll
mips64ext.ll
mips64extins.ll
mips64fpimm0.ll
mips64fpldst.ll
mips64imm.ll
mips64instrs.ll
mips64intldst.ll
mips64lea.ll
mips64load-store-left-right.ll
mips64muldiv.ll
mips64shift.ll
mipslopat.ll
misha.ll
mno-ldc1-sdc1.ll [mips] Fix typos. 2013-09-07 01:14:42 +00:00
mul.ll
mulll.ll
mulull.ll
neg1.ll
nomips16.ll Fix a problem with dual mips16/mips32 mode. When the underlying processor 2013-08-30 19:40:56 +00:00
not1.ll
null.ll
o32_cc_byval.ll [mips] Set instruction itineraries of loads, stores and conditional moves. 2013-09-06 23:28:24 +00:00
o32_cc_vararg.ll
o32_cc.ll
optimize-fp-math.ll
or1.ll
powif64_16.ll Make sure we don't generate stubs for any of these functions because they 2013-09-01 04:12:59 +00:00
private.ll
ra-allocatable.ll
rdhwr-directives.ll
rem.ll
remat-immed-load.ll
remu.ll
return_address.ll
return-vector.ll
rotate.ll
sb1.ll
select.ll
selectcc.ll
seleq.ll
seleqk.ll
selgek.ll
selgt.ll
selle.ll
selltk.ll
selne.ll
selnek.ll
selpat.ll
selTBteqzCmpi.ll
selTBtnezCmpi.ll
selTBtnezSlti.ll
setcc-se.ll
seteq.ll
seteqz.ll
setge.ll
setgek.ll
setle.ll
setlt.ll
setltk.ll
setne.ll
setuge.ll
setugt.ll
setule.ll
setult.ll
setultk.ll
sh1.ll
shift-parts.ll
sint-fp-store_pattern.ll
sitofp-selectcc-opt.ll
sll1.ll
sll2.ll
small-section-reserve-gp.ll
spill-copy-acreg.ll
sra1.ll
sra2.ll
srl1.ll
srl2.ll
stackcoloring.ll
stacksize.ll
stchar.ll
stldst.ll
sub1.ll
sub2.ll
swzero.ll
tailcall.ll
tls16_2.ll
tls16.ll
tls-alias.ll
tls-models.ll
tls.ll
tnaked.ll
trap1.ll
trap.ll
uitofp.ll
ul1.ll
unalignedload.ll
vector-load-store.ll
vector-setcc.ll
weak.ll
xor1.ll
zeroreg.ll