llvm-6502/lib/CodeGen/SelectionDAG
Dan Gohman 532dc2e1f2 Change getCopyToParts and getCopyFromParts to always use target-endian
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 20:59:04 +00:00
..
CallingConvLower.cpp add isVarArg to CCState 2007-06-19 00:11:09 +00:00
DAGCombiner.cpp Fix this warning: 2007-07-09 16:16:34 +00:00
LegalizeDAG.cpp Fix for PR 1505 (and 1489). Rewrite X87 register 2007-07-03 00:53:03 +00:00
Makefile
ScheduleDAG.cpp Change CalculateHeights and CalculateDepths to be non-recursive. 2007-07-06 01:37:28 +00:00
ScheduleDAGList.cpp switch the sched unit map over to use a DenseMap instead of std::map. This 2007-02-03 01:34:13 +00:00
ScheduleDAGRRList.cpp Remove unused variables. 2007-06-29 21:42:03 +00:00
ScheduleDAGSimple.cpp Removed tabs everywhere except autogenerated & external files. Add make 2007-04-16 18:10:23 +00:00
SelectionDAG.cpp Make the debug string for ISD::MERGE_VALUES consistent with the others. 2007-07-05 20:15:43 +00:00
SelectionDAGISel.cpp Change getCopyToParts and getCopyFromParts to always use target-endian 2007-07-09 20:59:04 +00:00
SelectionDAGPrinter.cpp Make chain dependencies blue, in addition to being dashed. 2007-06-18 15:30:16 +00:00
TargetLowering.cpp Initialize the IndexedModeActions array with memset before 2007-07-09 20:49:44 +00:00