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893e1c90a0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
307 lines
9.8 KiB
C++
307 lines
9.8 KiB
C++
//===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "PPCHazardRecognizers.h"
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// PowerPC 970 Hazard Recognizer
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//
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// This models the dispatch group formation of the PPC970 processor. Dispatch
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// groups are bundles of up to five instructions that can contain various mixes
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// of instructions. The PPC970 can dispatch a peak of 4 non-branch and one
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// branch instruction per-cycle.
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//
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// There are a number of restrictions to dispatch group formation: some
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// instructions can only be issued in the first slot of a dispatch group, & some
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// instructions fill an entire dispatch group. Additionally, only branches can
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// issue in the 5th (last) slot.
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//
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// Finally, there are a number of "structural" hazards on the PPC970. These
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// conditions cause large performance penalties due to misprediction, recovery,
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// and replay logic that has to happen. These cases include setting a CTR and
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// branching through it in the same dispatch group, and storing to an address,
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// then loading from the same address within a dispatch group. To avoid these
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// conditions, we insert no-op instructions when appropriate.
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//
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// FIXME: This is missing some significant cases:
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// 1. Modeling of microcoded instructions.
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// 2. Handling of serialized operations.
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// 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
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//
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PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
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: TII(tii) {
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::EndDispatchGroup() {
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DEBUG(errs() << "=== Start of dispatch group\n");
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NumIssued = 0;
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// Structural hazard info.
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HasCTRSet = false;
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NumStores = 0;
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}
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PPCII::PPC970_Unit
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PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
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bool &isFirst, bool &isSingle,
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bool &isCracked,
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bool &isLoad, bool &isStore) {
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if ((int)Opcode >= 0) {
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isFirst = isSingle = isCracked = isLoad = isStore = false;
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return PPCII::PPC970_Pseudo;
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}
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Opcode = ~Opcode;
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const TargetInstrDesc &TID = TII.get(Opcode);
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isLoad = TID.mayLoad();
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isStore = TID.mayStore();
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unsigned TSFlags = TID.TSFlags;
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isFirst = TSFlags & PPCII::PPC970_First;
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isSingle = TSFlags & PPCII::PPC970_Single;
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isCracked = TSFlags & PPCII::PPC970_Cracked;
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return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
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}
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/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
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/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
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bool PPCHazardRecognizer970::
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isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
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for (unsigned i = 0, e = NumStores; i != e; ++i) {
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// Handle exact and commuted addresses.
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if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
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return true;
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if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
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return true;
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// Okay, we don't have an exact match, if this is an indexed offset, see if
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// we have overlap (which happens during fp->int conversion for example).
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if (StorePtr2[i] == Ptr2) {
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if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
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if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
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// Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
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// to see if the load and store actually overlap.
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int StoreOffs = StoreOffset->getZExtValue();
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int LoadOffs = LoadOffset->getZExtValue();
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if (StoreOffs < LoadOffs) {
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if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
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} else {
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if (int(LoadOffs+LoadSize) > StoreOffs) return true;
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}
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}
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}
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}
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return false;
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}
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/// getHazardType - We return hazard for any non-branch instruction that would
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/// terminate terminate the dispatch group. We turn NoopHazard for any
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/// instructions that wouldn't terminate the dispatch group that would cause a
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/// pipeline flush.
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ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
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getHazardType(SUnit *SU) {
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const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
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bool isFirst, isSingle, isCracked, isLoad, isStore;
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PPCII::PPC970_Unit InstrType =
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GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
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isLoad, isStore);
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if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
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unsigned Opcode = Node->getMachineOpcode();
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// We can only issue a PPC970_First/PPC970_Single instruction (such as
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// crand/mtspr/etc) if this is the first cycle of the dispatch group.
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if (NumIssued != 0 && (isFirst || isSingle))
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return Hazard;
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// If this instruction is cracked into two ops by the decoder, we know that
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// it is not a branch and that it cannot issue if 3 other instructions are
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// already in the dispatch group.
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if (isCracked && NumIssued > 2)
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return Hazard;
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switch (InstrType) {
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default: llvm_unreachable("Unknown instruction type!");
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case PPCII::PPC970_FXU:
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case PPCII::PPC970_LSU:
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case PPCII::PPC970_FPU:
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case PPCII::PPC970_VALU:
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case PPCII::PPC970_VPERM:
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// We can only issue a branch as the last instruction in a group.
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if (NumIssued == 4) return Hazard;
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break;
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case PPCII::PPC970_CRU:
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// We can only issue a CR instruction in the first two slots.
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if (NumIssued >= 2) return Hazard;
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break;
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case PPCII::PPC970_BRU:
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break;
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}
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// Do not allow MTCTR and BCTRL to be in the same dispatch group.
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if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
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return NoopHazard;
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// If this is a load following a store, make sure it's not to the same or
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// overlapping address.
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if (isLoad && NumStores) {
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unsigned LoadSize;
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switch (Opcode) {
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default: llvm_unreachable("Unknown load!");
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case PPC::LBZ: case PPC::LBZU:
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case PPC::LBZX:
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case PPC::LBZ8: case PPC::LBZU8:
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case PPC::LBZX8:
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case PPC::LVEBX:
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LoadSize = 1;
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break;
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case PPC::LHA: case PPC::LHAU:
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case PPC::LHAX:
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case PPC::LHZ: case PPC::LHZU:
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case PPC::LHZX:
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case PPC::LVEHX:
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case PPC::LHBRX:
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case PPC::LHA8: case PPC::LHAU8:
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case PPC::LHAX8:
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case PPC::LHZ8: case PPC::LHZU8:
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case PPC::LHZX8:
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LoadSize = 2;
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break;
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case PPC::LFS: case PPC::LFSU:
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case PPC::LFSX:
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case PPC::LWZ: case PPC::LWZU:
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case PPC::LWZX:
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case PPC::LWA:
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case PPC::LWAX:
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case PPC::LVEWX:
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case PPC::LWBRX:
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case PPC::LWZ8:
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case PPC::LWZX8:
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LoadSize = 4;
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break;
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case PPC::LFD: case PPC::LFDU:
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case PPC::LFDX:
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case PPC::LD: case PPC::LDU:
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case PPC::LDX:
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LoadSize = 8;
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break;
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case PPC::LVX:
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case PPC::LVXL:
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LoadSize = 16;
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break;
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}
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if (isLoadOfStoredAddress(LoadSize,
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Node->getOperand(0), Node->getOperand(1)))
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return NoopHazard;
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}
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return NoHazard;
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}
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void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
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const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
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bool isFirst, isSingle, isCracked, isLoad, isStore;
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PPCII::PPC970_Unit InstrType =
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GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
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isLoad, isStore);
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if (InstrType == PPCII::PPC970_Pseudo) return;
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unsigned Opcode = Node->getMachineOpcode();
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// Update structural hazard information.
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if (Opcode == PPC::MTCTR) HasCTRSet = true;
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// Track the address stored to.
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if (isStore) {
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unsigned ThisStoreSize;
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switch (Opcode) {
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default: llvm_unreachable("Unknown store instruction!");
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case PPC::STB: case PPC::STB8:
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case PPC::STBU: case PPC::STBU8:
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case PPC::STBX: case PPC::STBX8:
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case PPC::STVEBX:
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ThisStoreSize = 1;
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break;
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case PPC::STH: case PPC::STH8:
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case PPC::STHU: case PPC::STHU8:
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case PPC::STHX: case PPC::STHX8:
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case PPC::STVEHX:
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case PPC::STHBRX:
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ThisStoreSize = 2;
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break;
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case PPC::STFS:
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case PPC::STFSU:
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case PPC::STFSX:
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case PPC::STWX: case PPC::STWX8:
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case PPC::STWUX:
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case PPC::STW: case PPC::STW8:
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case PPC::STWU: case PPC::STWU8:
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case PPC::STVEWX:
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case PPC::STFIWX:
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case PPC::STWBRX:
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ThisStoreSize = 4;
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break;
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case PPC::STD_32:
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case PPC::STDX_32:
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case PPC::STD:
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case PPC::STDU:
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case PPC::STFD:
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case PPC::STFDX:
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case PPC::STDX:
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case PPC::STDUX:
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ThisStoreSize = 8;
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break;
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case PPC::STVX:
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case PPC::STVXL:
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ThisStoreSize = 16;
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break;
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}
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StoreSize[NumStores] = ThisStoreSize;
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StorePtr1[NumStores] = Node->getOperand(1);
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StorePtr2[NumStores] = Node->getOperand(2);
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++NumStores;
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}
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if (InstrType == PPCII::PPC970_BRU || isSingle)
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NumIssued = 4; // Terminate a d-group.
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++NumIssued;
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// If this instruction is cracked into two ops by the decoder, remember that
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// we issued two pieces.
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if (isCracked)
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++NumIssued;
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if (NumIssued == 5)
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::AdvanceCycle() {
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assert(NumIssued < 5 && "Illegal dispatch group!");
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++NumIssued;
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if (NumIssued == 5)
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EndDispatchGroup();
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}
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