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https://github.com/c64scene-ar/llvm-6502.git
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6159873e46
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27309 91177308-0d34-0410-b5e6-96231b3b80d8
221 lines
11 KiB
TableGen
221 lines
11 KiB
TableGen
//===- IntrinsicsX86.td - Defines X86 intrinsics -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the X86-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SSE1
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// Arithmetic ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
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[InstrNoMem]>;
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def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
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[InstrNoMem]>;
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def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
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[InstrNoMem]>;
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def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
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[InstrNoMem]>;
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def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
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[InstrNoMem]>;
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def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
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[InstrNoMem]>;
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def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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}
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// Comparison ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_cmp_ss :
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>;
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def int_x86_sse_cmp_ps :
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>;
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}
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// Conversion ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">,
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Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,
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Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
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def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
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Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse_cvttps2pi : GCCBuiltin<"__builtin_ia32_cvttps2pi">,
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Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [InstrNoMem]>;
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def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
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Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [InstrNoMem]>;
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def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [InstrNoMem]>;
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}
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// SIMD load ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_loadh_ps : GCCBuiltin<"__builtin_ia32_loadhps">,
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Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
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def int_x86_sse_loadl_ps : GCCBuiltin<"__builtin_ia32_loadlps">,
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Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
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def int_x86_sse_loadu_ps : GCCBuiltin<"__builtin_ia32_loadups">,
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Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
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}
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// SIMD store ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_storeh_ps : GCCBuiltin<"__builtin_ia32_storehps">,
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Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
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def int_x86_sse_storel_ps : GCCBuiltin<"__builtin_ia32_storelps">,
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Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
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def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
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Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
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}
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// Cacheability support ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
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Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>;
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def int_x86_sse_movntq : GCCBuiltin<"__builtin_ia32_movntq">,
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Intrinsic<[llvm_ptr_ty, llvm_v2i32_ty], [IntrWriteMem]>;
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def int_x86_sse_movntps : GCCBuiltin<"__builtin_ia32_movntps">,
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Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
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def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
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Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
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}
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// Control register.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_stmxcsr : GCCBuiltin<"__builtin_ia32_stmxcsr">,
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Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
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def int_x86_sse_ldmxcsr : GCCBuiltin<"__builtin_ia32_ldmxcsr">,
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Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
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}
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// Misc.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">,
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Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// SSE2
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// Arithmetic ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
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[InstrNoMem]>;
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def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
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[InstrNoMem]>;
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def int_x86_sse2_rcp_sd : GCCBuiltin<"__builtin_ia32_rcpsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
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[InstrNoMem]>;
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def int_x86_sse2_rcp_pd : GCCBuiltin<"__builtin_ia32_rcppd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
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[InstrNoMem]>;
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def int_x86_sse2_rsqrt_sd : GCCBuiltin<"__builtin_ia32_rsqrtsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
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[InstrNoMem]>;
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def int_x86_sse2_rsqrt_pd : GCCBuiltin<"__builtin_ia32_rsqrtpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
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[InstrNoMem]>;
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def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_min_pd : GCCBuiltin<"__builtin_ia32_minpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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}
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// Misc.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [InstrNoMem]>;
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def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
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Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_v4i32_ty], [InstrNoMem]>;
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def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
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Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
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llvm_v8i16_ty], [InstrNoMem]>;
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def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
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Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
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Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// SSE3
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// Horizontal ops.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [InstrNoMem]>;
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def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [InstrNoMem]>;
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}
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