Andrew Lenharth f87e7931fd support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27370 91177308-0d34-0410-b5e6-96231b3b80d8		2006-04-03 04:19:17 +00:00
..
.cvsignore
Alpha.h
Alpha.td	Alpha Scheduling classes	2006-03-09 17:16:45 +00:00
AlphaAsmPrinter.cpp	Add support for 'special' llvm globals like debug info and static ctors/dtors.	2006-03-09 06:14:35 +00:00
AlphaCodeEmitter.cpp	Add explicit #includes of <iostream>	2006-01-22 23:41:00 +00:00
AlphaInstrFormats.td	Alpha Scheduling classes	2006-03-09 17:16:45 +00:00
AlphaInstrInfo.cpp	these are copies too	2006-03-09 18:18:51 +00:00
AlphaInstrInfo.h	isStoreToStackSlot	2006-02-03 03:07:37 +00:00
AlphaInstrInfo.td	support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4	2006-04-03 04:19:17 +00:00
AlphaISelDAGToDAG.cpp	support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4	2006-04-03 04:19:17 +00:00
AlphaISelLowering.cpp	mul by const conversion sequences. more coming soon	2006-04-03 03:18:59 +00:00
AlphaISelLowering.h	Alpha Scheduling classes	2006-03-09 17:16:45 +00:00
AlphaJITInfo.cpp	Remove a 'using namespace std'.	2006-01-01 22:20:31 +00:00
AlphaJITInfo.h
AlphaRegisterInfo.cpp	Expose base register for DwarfWriter. Refactor code accordingly.	2006-03-28 13:48:33 +00:00
AlphaRegisterInfo.h	Expose base register for DwarfWriter. Refactor code accordingly.	2006-03-28 13:48:33 +00:00
AlphaRegisterInfo.td	Add dwarf register numbering to register data.	2006-03-24 21:15:58 +00:00
AlphaRelocations.h
AlphaSchedule.td	Alpha Scheduling classes	2006-03-09 17:16:45 +00:00
AlphaSubtarget.cpp	Give full control of subtarget features over to table generated code.	2005-10-26 17:30:34 +00:00
AlphaSubtarget.h	Alpha Scheduling classes	2006-03-09 17:16:45 +00:00
AlphaTargetMachine.cpp	Eliminate IntrinsicLowering from TargetMachine.	2006-03-23 05:43:16 +00:00
AlphaTargetMachine.h	Eliminate IntrinsicLowering from TargetMachine.	2006-03-23 05:43:16 +00:00
Makefile