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and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
356 lines
12 KiB
C++
356 lines
12 KiB
C++
//===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Perform peephole optimizations on the machine code:
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//
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// - Optimize Extensions
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//
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// Optimization of sign / zero extension instructions. It may be extended to
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// handle other instructions with similar properties.
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//
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// On some targets, some instructions, e.g. X86 sign / zero extension, may
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// leave the source value in the lower part of the result. This optimization
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// will replace some uses of the pre-extension value with uses of the
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// sub-register of the results.
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//
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// - Optimize Comparisons
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//
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// Optimization of comparison instructions. For instance, in this code:
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//
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// sub r1, 1
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// cmp r1, 0
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// bz L1
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//
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// If the "sub" instruction all ready sets (or could be modified to set) the
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// same flag that the "cmp" instruction sets and that "bz" uses, then we can
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// eliminate the "cmp" instruction.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "peephole-opt"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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// Optimize Extensions
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static cl::opt<bool>
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Aggressive("aggressive-ext-opt", cl::Hidden,
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cl::desc("Aggressive extension optimization"));
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static cl::opt<bool>
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DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
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cl::desc("Disable the peephole optimizer"));
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STATISTIC(NumReuse, "Number of extension results reused");
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STATISTIC(NumEliminated, "Number of compares eliminated");
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STATISTIC(NumImmFold, "Number of move immediate foled");
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namespace {
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class PeepholeOptimizer : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT; // Machine dominator tree
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public:
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static char ID; // Pass identification
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PeepholeOptimizer() : MachineFunctionPass(ID) {
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initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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if (Aggressive) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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}
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private:
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bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
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bool OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &LocalMIs);
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bool isMoveImmediate(MachineInstr *MI,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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bool FoldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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};
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}
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char PeepholeOptimizer::ID = 0;
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INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
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"Peephole Optimizations", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
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"Peephole Optimizations", false, false)
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FunctionPass *llvm::createPeepholeOptimizerPass() {
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return new PeepholeOptimizer();
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}
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/// OptimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
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/// a single register and writes a single register and it does not modify the
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/// source, and if the source value is preserved as a sub-register of the
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/// result, then replace all reachable uses of the source with the subreg of the
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/// result.
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///
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/// Do not generate an EXTRACT that is used only in a debug use, as this changes
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/// the code. Since this code does not currently share EXTRACTs, just ignore all
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/// debug uses.
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bool PeepholeOptimizer::
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OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
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unsigned SrcReg, DstReg, SubIdx;
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if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
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return false;
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg))
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return false;
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MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
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if (++UI == MRI->use_nodbg_end())
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// No other uses.
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return false;
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// The source has other uses. See if we can replace the other uses with use of
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// the result of the extension.
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SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
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UI = MRI->use_nodbg_begin(DstReg);
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for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
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UI != UE; ++UI)
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ReachedBBs.insert(UI->getParent());
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// Uses that are in the same BB of uses of the result of the instruction.
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SmallVector<MachineOperand*, 8> Uses;
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// Uses that the result of the instruction can reach.
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SmallVector<MachineOperand*, 8> ExtendedUses;
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bool ExtendLife = true;
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UI = MRI->use_nodbg_begin(SrcReg);
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for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
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UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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MachineInstr *UseMI = &*UI;
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if (UseMI == MI)
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continue;
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if (UseMI->isPHI()) {
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ExtendLife = false;
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continue;
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}
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// It's an error to translate this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
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//
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// into this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1027 = COPY %reg1025:4
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// %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
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//
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// The problem here is that SUBREG_TO_REG is there to assert that an
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// implicit zext occurs. It doesn't insert a zext instruction. If we allow
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// the COPY here, it will give us the value after the <sext>, not the
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// original value of %reg1024 before <sext>.
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if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
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continue;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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// Local uses that come after the extension.
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if (!LocalMIs.count(UseMI))
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Uses.push_back(&UseMO);
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} else if (ReachedBBs.count(UseMBB)) {
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// Non-local uses where the result of the extension is used. Always
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// replace these unless it's a PHI.
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Uses.push_back(&UseMO);
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} else if (Aggressive && DT->dominates(MBB, UseMBB)) {
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// We may want to extend the live range of the extension result in order
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// to replace these uses.
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ExtendedUses.push_back(&UseMO);
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} else {
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// Both will be live out of the def MBB anyway. Don't extend live range of
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// the extension result.
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ExtendLife = false;
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break;
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}
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}
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if (ExtendLife && !ExtendedUses.empty())
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// Extend the liveness of the extension result.
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std::copy(ExtendedUses.begin(), ExtendedUses.end(),
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std::back_inserter(Uses));
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// Now replace all uses.
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bool Changed = false;
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if (!Uses.empty()) {
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SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
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// Look for PHI uses of the extended result, we don't want to extend the
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// liveness of a PHI input. It breaks all kinds of assumptions down
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// stream. A PHI use is expected to be the kill of its source values.
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UI = MRI->use_nodbg_begin(DstReg);
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for (MachineRegisterInfo::use_nodbg_iterator
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UE = MRI->use_nodbg_end(); UI != UE; ++UI)
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if (UI->isPHI())
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PHIBBs.insert(UI->getParent());
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const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
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for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
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MachineOperand *UseMO = Uses[i];
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MachineInstr *UseMI = UseMO->getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (PHIBBs.count(UseMBB))
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continue;
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unsigned NewVR = MRI->createVirtualRegister(RC);
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BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
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TII->get(TargetOpcode::COPY), NewVR)
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.addReg(DstReg, 0, SubIdx);
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UseMO->setReg(NewVR);
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++NumReuse;
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Changed = true;
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}
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}
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return Changed;
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}
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/// OptimizeCmpInstr - If the instruction is a compare and the previous
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/// instruction it's comparing against all ready sets (or could be modified to
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/// set) the same flag as the compare, then we can remove the comparison and use
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/// the flag from the previous instruction.
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bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
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MachineBasicBlock *MBB){
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// If this instruction is a comparison against zero and isn't comparing a
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// physical register, we can try to optimize it.
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unsigned SrcReg;
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int CmpMask, CmpValue;
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if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg))
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return false;
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// Attempt to optimize the comparison instruction.
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if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI)) {
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++NumEliminated;
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return true;
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}
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return false;
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}
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bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isMoveImmediate())
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return false;
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if (TID.getNumDefs() != 1)
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return false;
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unsigned Reg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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ImmDefMIs.insert(std::make_pair(Reg, MI));
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ImmDefRegs.insert(Reg);
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return true;
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}
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return false;
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}
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/// FoldImmediate - Try folding register operands that are defined by move
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/// immediate instructions, i.e. a trivial constant folding optimization, if
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/// and only if the def and use are in the same BB.
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bool PeepholeOptimizer::FoldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallSet<unsigned, 4> &ImmDefRegs,
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DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
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for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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if (ImmDefRegs.count(Reg) == 0)
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continue;
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DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
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assert(II != ImmDefMIs.end());
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if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
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++NumImmFold;
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return true;
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}
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}
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return false;
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}
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bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
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if (DisablePeephole)
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return false;
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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MRI = &MF.getRegInfo();
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DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : 0;
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bool Changed = false;
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SmallPtrSet<MachineInstr*, 8> LocalMIs;
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SmallSet<unsigned, 4> ImmDefRegs;
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DenseMap<unsigned, MachineInstr*> ImmDefMIs;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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bool SeenMoveImm = false;
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LocalMIs.clear();
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ImmDefRegs.clear();
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ImmDefMIs.clear();
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for (MachineBasicBlock::iterator
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MII = I->begin(), MIE = I->end(); MII != MIE; ) {
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MachineInstr *MI = &*MII++;
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LocalMIs.insert(MI);
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if (MI->getDesc().hasUnmodeledSideEffects())
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continue;
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if (MI->getDesc().isCompare()) {
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Changed |= OptimizeCmpInstr(MI, MBB);
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} else if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
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SeenMoveImm = true;
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} else {
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Changed |= OptimizeExtInstr(MI, MBB, LocalMIs);
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if (SeenMoveImm)
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Changed |= FoldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
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}
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}
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}
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return Changed;
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}
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