mirror of
https://github.com/c64scene-ar/llvm-6502.git
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47734db936
This is another prerequisite for frame-to-frame MVC copies. I'll commit the patch that makes use of the slot separately. The downside of trying to test many corner cases with each of the available addressing modes is that a fair few tests need to account for the new frame layout. I do still think it's useful to have all these tests though, since it's something that wouldn't get much coverage otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185698 91177308-0d34-0410-b5e6-96231b3b80d8
154 lines
4.5 KiB
LLVM
154 lines
4.5 KiB
LLVM
; Test the handling of the frame pointer (%r11).
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck %s
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; We should always initialise %r11 when FP elimination is disabled.
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; We don't need to allocate any more than the caller-provided 160-byte
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; area though.
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define i32 @f1(i32 %x) {
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; CHECK: f1:
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; CHECK: stmg %r11, %r15, 88(%r15)
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; CHECK: .cfi_offset %r11, -72
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; CHECK: .cfi_offset %r15, -40
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; CHECK-NOT: ag
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; CHECK: lgr %r11, %r15
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; CHECK: .cfi_def_cfa_register %r11
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; CHECK: lmg %r11, %r15, 88(%r11)
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; CHECK: br %r14
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%y = add i32 %x, 1
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ret i32 %y
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}
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; Make sure that frame accesses after the initial allocation are relative
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; to %r11 rather than %r15.
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define void @f2(i64 %x) {
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; CHECK: f2:
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; CHECK: stmg %r11, %r15, 88(%r15)
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; CHECK: .cfi_offset %r11, -72
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; CHECK: .cfi_offset %r15, -40
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; CHECK: aghi %r15, -168
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; CHECK: .cfi_def_cfa_offset 328
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; CHECK: lgr %r11, %r15
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; CHECK: .cfi_def_cfa_register %r11
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; CHECK: stg %r2, 160(%r11)
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; CHECK: lmg %r11, %r15, 256(%r11)
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; CHECK: br %r14
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%y = alloca i64, align 8
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store volatile i64 %x, i64* %y
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ret void
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}
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; This function should require all GPRs but no other spill slots.
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; It shouldn't need to allocate its own frame.
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define void @f3(i32 *%ptr) {
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; CHECK: f3:
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; CHECK: stmg %r6, %r15, 48(%r15)
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; CHECK-NOT: %r15
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; CHECK-NOT: %r11
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; CHECK: .cfi_offset %r6, -112
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; CHECK: .cfi_offset %r7, -104
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; CHECK: .cfi_offset %r8, -96
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; CHECK: .cfi_offset %r9, -88
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; CHECK: .cfi_offset %r10, -80
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; CHECK: .cfi_offset %r11, -72
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; CHECK: .cfi_offset %r12, -64
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; CHECK: .cfi_offset %r13, -56
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; CHECK: .cfi_offset %r14, -48
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; CHECK: .cfi_offset %r15, -40
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; CHECK-NOT: ag
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; CHECK: lgr %r11, %r15
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; CHECK: .cfi_def_cfa_register %r11
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; ...main function body...
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; CHECK-NOT: %r15
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; CHECK-NOT: %r11
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; CHECK: st {{.*}}, 4(%r2)
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; CHECK: lmg %r6, %r15, 48(%r11)
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; CHECK: br %r14
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%l0 = load volatile i32 *%ptr
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%l1 = load volatile i32 *%ptr
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%l3 = load volatile i32 *%ptr
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%l4 = load volatile i32 *%ptr
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%l5 = load volatile i32 *%ptr
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%l6 = load volatile i32 *%ptr
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%l7 = load volatile i32 *%ptr
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%l8 = load volatile i32 *%ptr
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%l9 = load volatile i32 *%ptr
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%l10 = load volatile i32 *%ptr
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%l12 = load volatile i32 *%ptr
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%l13 = load volatile i32 *%ptr
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%l14 = load volatile i32 *%ptr
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%add0 = add i32 %l0, %l0
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%add1 = add i32 %l1, %add0
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%add3 = add i32 %l3, %add1
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%add4 = add i32 %l4, %add3
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%add5 = add i32 %l5, %add4
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%add6 = add i32 %l6, %add5
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%add7 = add i32 %l7, %add6
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%add8 = add i32 %l8, %add7
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%add9 = add i32 %l9, %add8
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%add10 = add i32 %l10, %add9
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%add12 = add i32 %l12, %add10
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%add13 = add i32 %l13, %add12
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%add14 = add i32 %l14, %add13
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store volatile i32 %add0, i32 *%ptr
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store volatile i32 %add1, i32 *%ptr
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store volatile i32 %add3, i32 *%ptr
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store volatile i32 %add4, i32 *%ptr
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store volatile i32 %add5, i32 *%ptr
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store volatile i32 %add6, i32 *%ptr
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store volatile i32 %add7, i32 *%ptr
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store volatile i32 %add8, i32 *%ptr
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store volatile i32 %add9, i32 *%ptr
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store volatile i32 %add10, i32 *%ptr
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store volatile i32 %add12, i32 *%ptr
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store volatile i32 %add13, i32 *%ptr
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%final = getelementptr i32 *%ptr, i32 1
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store volatile i32 %add14, i32 *%final
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ret void
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}
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; The largest frame for which the LMG is in range. This frame has two
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; emergency spill slots at 160(%r11), so create a frame of size 524192
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; by allocating (524192 - 176) / 8 = 65502 doublewords.
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define void @f4(i64 %x) {
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; CHECK: f4:
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; CHECK: stmg %r11, %r15, 88(%r15)
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; CHECK: .cfi_offset %r11, -72
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; CHECK: .cfi_offset %r15, -40
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; CHECK: agfi %r15, -524192
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; CHECK: .cfi_def_cfa_offset 524352
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; CHECK: lgr %r11, %r15
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; CHECK: .cfi_def_cfa_register %r11
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; CHECK: stg %r2, 176(%r11)
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; CHECK-NOT: ag
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; CHECK: lmg %r11, %r15, 524280(%r11)
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; CHECK: br %r14
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%y = alloca [65502 x i64], align 8
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%ptr = getelementptr inbounds [65502 x i64]* %y, i64 0, i64 0
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store volatile i64 %x, i64* %ptr
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ret void
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}
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; The next frame size larger than f4.
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define void @f5(i64 %x) {
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; CHECK: f5:
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; CHECK: stmg %r11, %r15, 88(%r15)
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; CHECK: .cfi_offset %r11, -72
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; CHECK: .cfi_offset %r15, -40
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; CHECK: agfi %r15, -524200
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; CHECK: .cfi_def_cfa_offset 524360
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; CHECK: lgr %r11, %r15
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; CHECK: .cfi_def_cfa_register %r11
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; CHECK: stg %r2, 176(%r11)
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; CHECK: aghi %r11, 8
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; CHECK: lmg %r11, %r15, 524280(%r11)
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; CHECK: br %r14
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%y = alloca [65503 x i64], align 8
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%ptr = getelementptr inbounds [65503 x i64]* %y, i64 0, i64 0
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store volatile i64 %x, i64* %ptr
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ret void
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}
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; The tests above establish that %r11 is handled like %r15 for LMG.
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; Rely on the %r15-based tests in frame-08.ll for other cases.
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